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ADM1073ARUZ-REEL7 PDF预览

ADM1073ARUZ-REEL7

更新时间： 2024-02-09 08:46:50
品牌 Logo 应用领域
亚德诺 - ADI 电源电路电源管理电路光电二极管信息通信管理控制器
页数 文件大小 规格书
24页 376K
描述
Full-Feature −48 V Hot Swap Controller

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ADM1073ARUZ-REEL7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：14
Reach Compliance Code：unknown风险等级：5.15
其他特性：OPERATES ON NEGATIVE OPERATING VOLTAGE RANGE OF -200 TO -18 WITH -48 NOM VOLTAGE可调阈值：NO
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：R-PDSO-G14
JESD-609代码：e3长度：5 mm
湿度敏感等级：1信道数量：1
功能数量：1端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260座面最大高度：1.2 mm
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：4.4 mmBase Number Matches：1

ADM1073ARUZ-REEL7 数据手册

 浏览型号ADM1073ARUZ-REEL7的Datasheet PDF文件第1页浏览型号ADM1073ARUZ-REEL7的Datasheet PDF文件第2页浏览型号ADM1073ARUZ-REEL7的Datasheet PDF文件第4页浏览型号ADM1073ARUZ-REEL7的Datasheet PDF文件第5页浏览型号ADM1073ARUZ-REEL7的Datasheet PDF文件第6页浏览型号ADM1073ARUZ-REEL7的Datasheet PDF文件第7页 
Data Sheet  
ADM1073  
GENERAL DESCRIPTION  
(continued from Page 1)  
(typically −36 V) is detected on the UV pin, or if greater than  
the overvoltage threshold (typically −80 V) is detected on the  
OV pin. The operating voltage window of the ADM1073 is  
programmable via resistor networks on the UV and OV pins.  
The hysteresis levels on the undervoltage and overvoltage  
detectors can also be altered (see the Undervoltage/Overvoltage  
Further control of the inrush current is provided by modulating  
the width of the pulses, depending on the drain-source voltage  
across the FET. This allows maximum charge transfer to the  
load capacitance while maintaining the FET in its safe operating  
area (SOA).  
The default duty cycle of the pulse train is 6%, decreasing to  
2.5% with maximum FET drain-source voltage, with a  
maximum of seven successive autorestarts. After seven  
successive autorestarts, the fault is latched and the part goes into  
shutdown, with the result that the external FET is disabled until  
SPLYGD  
Detection section). The  
output signal indicates when  
the backplane supply is within the externally programmable  
operating voltage range.  
Other functions include  
LATCHED  
the power is reset. The  
the seven retries are complete.  
output signal indicates when  
PWRGD  
•
output, which can be used to enable a power  
module (the DRAIN pin is monitored to determine when  
the load capacitance is fully charged)  
Further programmability is offered by allowing alteration of the  
default 6% ratio. An extra resistor between the TIMER pin and  
EE allows the ratio of on-time to off-time to be decreased,  
SHDN  
•
•
input to manually disable the GATE drive  
RESTART  
input to remotely initiate a 5 second shutdown  
V
The ADM1073 is fabricated using BiCMOS technology for  
minimal power consumption and is available in a 14-lead  
TSSOP package.  
while a resistor between TIMER and VIN allows the ratio to be  
increased.  
The ADM1073 has separate UV and OV pins for undervoltage  
and overvoltage detection. The FET is turned off, if a  
nontransient voltage less than the undervoltage threshold  
Rev. B | Page 3 of 24  
 
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