ADM1032
Table V. Configuration Register Bit Assignments
Power-On
Consecutive ALERT Register
This value written to this register determines how many out-of-
limit measurements must occur before an ALERT is generated.
The default value is that one out-of-limit measurement gener-
ates an ALERT. The max value that can be chosen is 4. The
purpose of this register is to allow the user to perform some filter-
ing of the output. This is particularly useful at the faster two
conversion rates where no averaging takes place.
Bit
Name
Function
Default
7
MASK1
0 = ALERT Enabled
1 = ALERT Masked
0 = Run
1 = Standby
Reserved
0
6
RUN/STOP
0
0
5–0
Table VII.
Conversion Rate Register
Number of “Out-of-Limit”
Measurements Required
The lowest four bits of this register are used to program the
conversion rate by dividing the internal oscillator clock by 1, 2,
4, 8, 16, 32, 64, 128, 256, 512, or 1024 to give conversion
times from 15.5 ms (code 0Ah) to 16 seconds (code 00h). This
register can be written to and read back over the SMBus. The
higher four bits of this register are unused and must be set to
zero. Use of slower conversion times greatly reduces the device
power consumption, as shown in Table VI.
Register Value
yxxx 000x
yxxx 001x
yxxx 011x
yxxx 111x
1
2
3
4
NOTES
x = Don’t care bit.
y = SMBus timeout bit. Default = 0. See SMBus section for more
information.
Table VI. Conversion Rate Register Codes
Average Supply Current
SERIAL BUS INTERFACE
Data
Conversion/sec
mA Typ at VDD = 5.5 V
Control of the ADM1032 is carried out via the serial bus. The
ADM1032 is connected to this bus as a slave device, under the
control of a master device.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0B to FFh
0.0625
0.125
0.25
0.5
1
2
4
8
0.17
0.20
0.21
0.24
0.29
0.40
0.61
1.1
There is a programmable SMBus timeout. When this is enabled
the SMBus will timeout after typically 25 ms of no activity. How-
ever, this feature is not enabled by default. To enable it, set Bit 7
of the Consecutive Alert Register (Addr = 22h).
The ADM1032 supports Packet Error Checking (PEC) and its
use is optional. It is triggered by supplying the extra clock for the
PEC byte. The PEC byte is calculated using CRC-8. The Frame
Check Sequence (FCS) conforms to CRC-8 by the polynomial:
16
1.9
32
64
0.73
1.23
C(x) = x8 + x2 + x1 + 1
Reserved
Consult SMBus 1.1 specification for more information
(www.smbus.org).
Limit Registers
The ADM1032 has nine Limit Registers to store local and remote,
high, low, and THERM temperature limits. These registers can
be written to and read back over the SMBus.
ADDRESSING THE DEVICE
In general, every SMBus device has a 7-bit device address (except
for some devices that have extended, 10-bit addresses). When
the master device sends a device address over the bus, the slave
device with that address will respond. The ADM1032 is avail-
able with one device address, which is Hex 4C (1001 100).
The high limit registers perform a > comparison while the low
limit registers perform a < comparison. For example, if the high
limit register is programmed with 80°C, then measuring 81oC
will result in an alarm condition. If the Low Limit Register is
programmed with 0°C, measuring 0°C or lower will result in
Alarm condition. Exceeding either the Local or Remote THERM
limit asserts THERM low. A default hysteresis value of 10°C is
provided, which applies to both channels. This hysteresis may
be reprogrammed to any value after power up (Reg 0x21h).
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDATA, while the serial clock line SCLK remains
high. This indicates that an address/data stream will follow.
All slave peripherals connected to the serial bus respond to
the START condition, and shift in the next eight bits, con-
sisting of a 7-bit address (MSB first) plus an R/W bit, which
determines the direction of the data transfer, i.e., whether
data will be written to or read from the slave device.
One-Shot Register
The One-Shot Register is used to initiate a single conversion
and comparison cycle when the ADM1032 is in standby mode,
after which the device returns to standby. This is not a data
register as such, and it is the write operation that causes the
one-shot conversion. The data written to this address is irrel-
evant and is not stored. The conversion time on a single shot is
96 ms when the conversion rate is 16 conversions per second or
less. At 32 conversions per second the conversion time is 15.3 ms.
This is because averaging is disabled at the faster conversion rates
(32 and 64 conversions per second).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
REV. 0
–7–
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