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ADL5502ACBZ-P2 PDF预览

ADL5502ACBZ-P2

更新时间： 2024-02-23 15:41:15
品牌 Logo 应用领域
亚德诺 - ADI 电信集成电路蜂窝电话电路电信电路信息通信管理
页数 文件大小 规格书
14页 449K
描述
800 MHz to 3800 MHz Crest Factor Detector

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ADL5502ACBZ-P2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：8
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01风险等级：5.47
JESD-30 代码：S-PBGA-B8JESD-609代码：e1
长度：1.46 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：SQUARE封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：0.625 mm标称供电电压：3 V
表面贴装：YES技术：BICMOS
电信集成电路类型：RF AND BASEBAND CIRCUIT温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：1.46 mm
Base Number Matches：1

ADL5502ACBZ-P2 数据手册

 浏览型号ADL5502ACBZ-P2的Datasheet PDF文件第7页浏览型号ADL5502ACBZ-P2的Datasheet PDF文件第8页浏览型号ADL5502ACBZ-P2的Datasheet PDF文件第9页浏览型号ADL5502ACBZ-P2的Datasheet PDF文件第11页浏览型号ADL5502ACBZ-P2的Datasheet PDF文件第12页浏览型号ADL5502ACBZ-P2的Datasheet PDF文件第13页 
ADL5502  
Preliminary Technical Data  
APPLICATIONS  
BASIC CONNECTIONS  
Figure 17 shows the basic connections for the ADL5502. The  
device is powered by a single supply between 2.5 V and 3.5 V,  
with a quiescent current of 5 mA. The VPOS pin is decoupled  
using 100 pF and 0.1 ꢀF capacitors.  
Placing a single 75 ꢁ resistor at the RF input provides a  
broadband match of 50 Ohms. More precise resistive or  
reactive matches can be applied for narrow frequency band use  
(see impedance plot, Figure 7).  
Figure 17. Basic Connections for ADL5502  
The rms averaging can be augmented by placing additional  
capacitance at CFLT. The ac residual can be further reduced by  
increasing the output capacitance, COUT. The combination of  
the internal 100 Ω output resistance and COUT produce a low-  
pass filter to reduce output ripple of the VRMS output. Note  
that a minimum of 4.7 nF capacitive load should be kept on the  
RMS output.  
To operate the device in peak-hold mode, the control line must be  
temporally set to HI (reset or envelope mode) and then set back to  
LO (peak-hold mode). This allows the ADL5502 to be initialize to  
a known state.  
EVALUATION BOARD  
Figure 18 shows the schematic of the ADL5502 evaluation  
board. The board is powered by a single supply in the 2.5 V to  
3.5 V range. The power supply is decoupled by 100 pF and  
0.1 ꢀF capacitors. Table 4 details the various configuration  
options of the evaluation board. Figure 19 and Figure 20 show  
the component and circuit layouts of the evaluation board.  
The device is place in peak-hold mode by placing switch SW2 in  
the position closes to the “SW2” label. Envelope-tracking mode is  
possible by setting SW2 in the opposite switch position (away from  
the “SW2” label). A signal generator can drive the control mode  
via the SMA labeled CNTL (see Table 4 for more details).  
OPERATING IN PEAK-HOLD MODE  
The RF input has a broadband match of 50 Ohms using a single  
75 ꢁ resistor at R10. More precise matching at spot frequencies  
is possible using the pads for components C15, C16, and R10.  
To operate the device in peak-hold mode, the control line must be  
temporally set to HI (envelope mode) and then set back to LO  
(peak-hold mode). This allows the ADL5502 to be initialize to a  
known state.  
The two outputs, accessible via the SMAs labeled VRMS and  
VENV, provide the rms response and the envelope/peak-hold  
vmeasurement of the RF input power level. The device must be  
enabled by switching SW1 to HI (setting the switch to the  
position opposite that of the “SW1” label).  
For envelope mode or rms use only, the control line can simply be  
set to HI.  
Rev. PrD (04/20/2008) | Page 10 of 14  
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