ADF7025
Parameter
Min
Typ
Max
Unit
Test Conditions
CHANNEL FILTERING
Adjacent Channel Rejection
(Offset = 1 ꢀ LP Filter BW Setting)
27
40
43
−2
70
dB
dB
dB
dB
dB
Desired signal (38.4 kbps DR, 200 kHz FDEV,
300 KHz LP filter B/W) 6 dB above the
input sensitivity level, CW interferer power
level increased until BER = 10−3
Second Adjacent Channel Rejection
(Offset = 2 ꢀ LP Filter BW Setting)
Third Adjacent Channel Rejection
(Offset = 3 ꢀ LP Filter BW Setting)
Co-Channel Rejection
+24
Maximum rejection measured with CW
interferer at center of channel
Swept from 100 MHz to 2 GHz,
measured as channel rejection
Wideband Interference Rejection
BLOCKING
1 MHz
Desired signal (38.4 kbps DR, 200 kHz FDEV,
300 KHz LP filter B/W) 6 dB above the
input sensitivity level, CW interferer power
level increased until BER = 10−3
42
dB
dB
dB
dBm
Ω
2 MHz
51
10 MHz
64
12
Saturation (Maximum Input Level)
LNA Input Impedance
FSK mode, BER = 10−3
FRF = 915 MHz, RFIN to GND
FRF = 868 MHz
24 − j60
26 − j63
71 − j128
Ω
Ω
FRF = 433 MHz
RSSI
Range at Input
−100 to
−36
dBm
Linearity
2
3
150
dB
dB
µs
Absolute Accuracy
Response Time
PHASE-LOCKED LOOP
VCO Gain
65
MHz/V
MHz/V
dBc/Hz
902 MHz to 928 MHz band,
VCO adjust = 3, VCO_BIAS_SETTING = 12
862 MHz to 870 MHz band,
VCO adjust = 0, VCO_BIAS_SETTING = 10
PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,
FRF = 868 MHz, VCO_BIAS_SETTING = 10
83
Phase Noise (In-Band)
−89
Phase Noise (Out-of-Band)
Residual FM
PLL Settling Time
−110
128
40
dBc/Hz
Hz
µs
1 MHz offset
From 200 Hz to 20 kHz, FRF = 868MHz
Measured for a 10 MHz frequency step
to within 5 ppm accuracy,
PFD = 20 MHz, LBW = 50kHz
REFERENCE INPUT
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
Input Level
3.625
3.625
24
24
MHz
MHz
pF
ms
CMOS
levels
33
1.0
Using 33 pF load capacitors
TIMING INFORMATION
Chip Enabled to Regulator Ready
Crystal Oscillator Startup Time
Tx to Rx Turnaround Time
10
1
150 µs +
(5 ꢀ TBIT)
µs
ms
CREG = 100 nF
With 19.2 MHz XTAL
Time to synchronized data,
includes AGC settling
Rev. A | Page 5 of 44