ADF7012
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DV
DD
1
24
C
REG2
C
2
23
R
REG1
SET
CP
3
22 AGND
OUT
TSSOP
TxDATA
4
21 DV
20 RF
19 RF
DD
TxCLK
MUXOUT
DGND
5
OUT
GND
ADF7012
TOP VIEW
(Not to Scale)
6
7
18 VCO
IN
OSC1
8
17 C
VCO
OSC2
9
16 L2
15 L1
14 CE
13 LE
CLK
10
OUT
CLK 11
DATA 12
Figure 3.
Table 4. Pin Functional Descriptions
Pin No. Mnemonic Description
1
2
3
DVDD
CREG1
CPOUT
Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin.
A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor
improves regulator power-on time, but may cause higher spurious noise.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
4
5
TxDATA
TxCLK
Digital Data to Be Transmitted is inputted on this pin.
GFSK and GOOK only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the
ADF7012. The clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on
the falling edge of TxCLK. The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit.
6
MUXOUT
Provides the Lock_Detect Signal. This determines if the PLL is locked to the correct frequency and also monitors
battery voltage. Other signals include Regulator_Ready, which indicates the status of the serial interface regulator.
7
8
9
DGND
OSC1
OSC2
Ground for Digital Section.
The reference crystal should be connected between this pin and OSC2.
The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving
this pin with CMOS levels, and powering down the crystal oscillator bit in software.
10
11
12
13
14
15
CLKOUT
CLK
DATA
LE
A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive
several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1uA. Register values are
lost when CE is low and the part must be reprogrammed once CE is brought high.
Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the
value of the inductor to be connected between L1 and L2.
CE
L1
16
17
L2
CVCO
Connected to external printed or discrete inductor.
A 220 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012.
This capacitor is necessary to ensure stable VCO operation.
18
VCOIN
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The
higher the tuning voltage, the higher the output frequency.
19
20
RFGND
RFOUT
Ground for Output Stage of Transmitter.
The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output
should be impedance matched using suitable components to the desired load. See the PA Matching section.
21
DVDD
Voltage supply for VCO and PA section. This should have the same supply as DVDD Pin 1, and should be between
2.3 V and 3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin.
22
23
24
AGND
RSET
CREG2
Ground Pin for the RF Analog Circuitry.
External Resistor to set charge pump current and some internal bias currents. Use 3.6 kV as default.
Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves
regulator power-on time and phase noise, but may have stability issues over the supply and temperature.
Rev. 0 | Page 7 of 28
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