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ADF4350BCPZ PDF预览

ADF4350BCPZ

更新时间: 2024-02-18 14:21:28
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路信息通信管理
页数 文件大小 规格书
28页 700K
描述
Wideband Synthesizer with Integrated VCO

ADF4350BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:unknown风险等级:5.43
Is Samacsys:N模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:NOT APPLICABLE
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:COMMERCIAL
座面最大高度:1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:5 mmBase Number Matches:1

ADF4350BCPZ 数据手册

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ADF4350  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
24  
23  
22  
21  
20  
19  
18  
17  
V
V
R
A
CLK  
DATA  
LE  
CE  
SW  
1
2
REF  
PIN 1  
COM  
INDICATOR  
3
4
SET  
ADF4350  
GNDVCO  
5
6
7
8
V
TOP VIEW  
TUNE  
V
P
OUT  
(Not to Scale)  
TEM  
A
V
P
CP  
GNDVCO  
VCO  
CP  
GND  
NOTES  
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.  
Figure 3. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1
CLK  
DATA  
LE  
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high  
impedance CMOS input.  
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high  
impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register  
that is selected by the three LSBs.  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.  
A logic high on this pin powers up the device depending on the status of the power-down bits.  
2
3
4
CE  
5
6
SW  
VP  
Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode.  
Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to  
be placed as close as possible to this pin.  
7
CPOUT  
Charge Pump Output. When enabled, this provides ICP to the external loop filter. The output of the loop filter is  
connected to VTUNE to drive the internal VCO.  
8
9
10  
CPGND  
AGND  
AVDD  
Charge Pump Ground. This is the ground return pin for CPOUT  
Analog Ground. This is a ground return pin for AVDD.  
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are  
to be placed as close as possible to this pin. AVDD must have the same value as DVDD.  
.
11, 18, 21  
AGNDVCO  
VCO Analog Ground. These are the ground return pins for the VCO.  
12  
13  
RFOUTA+  
RFOUTA−  
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.  
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided  
down version is available.  
14  
RFOUTB+  
RFOUTB−  
VVCO  
Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down  
version is available.  
Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a  
divided down version is available.  
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane  
should be placed as close as possible to these pins. VVCO must have the same value as AVDD.  
Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as  
possible to this pin.  
15  
16, 17  
19  
TEMP  
VTUNE  
20  
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT  
output voltage.  
Rev. 0 | Page 7 of 28  
 

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