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ADF4252BCPZ-REEL7 PDF预览

ADF4252BCPZ-REEL7

更新时间： 2024-01-10 21:44:29
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
28页 467K
描述
PLL FREQUENCY SYNTHESIZER, 3000MHz, QCC24, MO-220-VGGD, LFCSP-24

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ADF4252BCPZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：MO-220-VGGD, LFCSP-24针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.14模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-XQCC-N24JESD-609代码：e0
长度：4 mm功能数量：1
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：VQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：0.9 mm
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：4 mmBase Number Matches：1

ADF4252BCPZ-REEL7 数据手册

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ADF4252  
PIN FUNCTION DESCRIPTIONS  
Mnemonic  
CPRF  
Function  
RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.  
RF Charge Pump Ground.  
CPGND1  
RFINA  
Input to the RF Prescaler. This small signal input is normally taken from the VCO.  
Complementary Input to the RF Prescaler.  
RFINB  
AGND1  
Analog Ground for the RF Synthesizer.  
MUXOUT  
This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference fre-  
quency to be accessed externally.  
REFIN  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of  
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.  
REFOUT  
DGND  
Reference Output.  
Digital Ground for the Fractional Interpolator.  
CLK  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the  
shift register on the CLK rising edge. This input is a high impedance CMOS input.  
DATA  
LE  
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a  
high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the  
seven latches, the latch being selected using the control bits.  
RSET  
Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship  
between ICP and RSET is  
1.6875  
RSET  
ICPmin  
=
Therefore, with RSET = 2.7 kΩ, ICPmin = 0.625 mA.  
Ground for the IF Synthesizer.  
AGND  
2
IFINB  
IFINA  
DVDD  
Complementary Input to the IF Prescaler.  
Input to the IF Prescaler. This small signal input is normally taken from the IF VCO.  
Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should  
be placed as close as possible to this pin. DVDD must have the same voltage as VDD1, VDD2, and VDD3.  
CPGND2  
CPIF  
IF Charge Pump Ground.  
IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.  
VP2  
IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible  
to this pin. This voltage should be greater than or equal to VDD2.  
V
V
V
DD2  
DD3  
DD1  
Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as  
possible to this pin. VDD2 has a value 3 V 10%. VDD2 must have the same voltage as VDD1, VDD3, and DVDD  
Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close  
as possible to this pin. VDD3 has a value 3 V 10%. VDD3 must have the same voltage as VDD1, VDD2, and DVDD  
Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close  
as possible to this pin. VDD1 has a value 3 V 10%. VDD1 must have the same voltage as VDD2, VDD3, and DVDD  
.
.
.
VP1  
RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible  
to this pin. This voltage should be greater than or equal to VDD1.  
REV. B  
–5–  
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