ADF4252
PIN FUNCTION DESCRIPTIONS
Mnemonic
CPRF
Function
RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.
RF Charge Pump Ground.
CPGND1
RFINA
Input to the RF Prescaler. This small signal input is normally taken from the VCO.
Complementary Input to the RF Prescaler.
RFINB
AGND1
Analog Ground for the RF Synthesizer.
MUXOUT
This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference fre-
quency to be accessed externally.
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.
REFOUT
DGND
Reference Output.
Digital Ground for the Fractional Interpolator.
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA
LE
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
seven latches, the latch being selected using the control bits.
RSET
Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship
between ICP and RSET is
1.6875
RSET
ICPmin
=
Therefore, with RSET = 2.7 kΩ, ICPmin = 0.625 mA.
Ground for the IF Synthesizer.
AGND
2
IFINB
IFINA
DVDD
Complementary Input to the IF Prescaler.
Input to the IF Prescaler. This small signal input is normally taken from the IF VCO.
Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. DVDD must have the same voltage as VDD1, VDD2, and VDD3.
CPGND2
CPIF
IF Charge Pump Ground.
IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.
VP2
IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
to this pin. This voltage should be greater than or equal to VDD2.
V
V
V
DD2
DD3
DD1
Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as
possible to this pin. VDD2 has a value 3 V 10%. VDD2 must have the same voltage as VDD1, VDD3, and DVDD
Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. VDD3 has a value 3 V 10%. VDD3 must have the same voltage as VDD1, VDD2, and DVDD
Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. VDD1 has a value 3 V 10%. VDD1 must have the same voltage as VDD2, VDD3, and DVDD
.
.
.
VP1
RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
to this pin. This voltage should be greater than or equal to VDD1.
REV. B
–5–