ADF4210/ADF4211/ADF4212/ADF4213
Parameter
B Version B Chips2 Unit
Test Conditions/Comments
POWER SUPPLIES
V
VDD
VP
DD1
2
2.7/5.5
VDD
VDD1/6.0
2.7/5.5
VDD
VDD1/6.0
V min/V max
V min/V max VDD1, VDD2 Յ VDD1, VDD2 Յ 6.0 V
1
1
I
I
I
DD (RF + IF)6
ADF4210
ADF4211
ADF4212
ADF4213
DD (RF Only)
ADF4210
ADF4211
ADF4212
ADF4213
DD (IF Only)
ADF4210
ADF4211
ADF4212
ADF4213
11.5
15.0
17.5
20
11.5
15.0
17.5
20
mA max
mA max
mA max
mA max
9.0 mA typical
11.0 mA typical
13.0 mA typical
15 mA typical
6.75
10
12.5
15
6.75
10
12.5
15
mA max
mA max
mA max
mA max
5.0 mA typical
7.0 mA typical
9.0 mA typical
11 mA typical
5.5
5.5
5.5
5.5
1.0
1
5.5
5.5
5.5
5.5
1.0
1
mA max
mA max
mA max
mA max
mA max
µA typ
4.5 mA typical
4.5 mA typical
4.5 mA typical
4.5 mA typical
IP (IP1 + IP2)
Low-Power Sleep Mode
TA = 25°C, 0.55 mA typical
NOISE CHARACTERISTICS
ADF4213 Phase Noise Floor7
–171
–164
–171
–164
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
Phase Noise Performance8
ADF4210/ADF4211, IF: 540 MHz Output9
ADF4212/ADF4213, IF: 900 MHz Output10
ADF4210/ADF4211, RF: 900 MHz Output10
ADF4212/ADF4213, RF: 900 MHz Output10
–91
–89
–89
–91
–91
–89
–89
–91
–85
–67
–88
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 1 kHz Offset and 200 kHz PFD Frequency
See Note 11
See Note 11
See Note 11
See Note 11
ADF4211/ADF4212, RF: 1750 MHz Output12 –85
ADF4211/ADF4212, RF: 1750 MHz Output13 –67
ADF4212/ADF4213, RF: 2400 MHz Output14 –88
Spurious Signals
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 1 MHz PFD Frequency
ADF4210/ADF4211, IF: 540 MHz Output9
ADF4212/ADF4213, IF: 900 MHz Output10
ADF4210/ADF4211, RF: 900 MHz Output10
ADF4212/ADF4213, RF: 900 MHz Output10
–88/–90
–88/–90
–90/–94
–90/–94
–90/–94
–80/–82
–65/–70
–80/–82
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
See Note 11
See Note 11
See Note 11
–90/–94
–90/–94
–90/–94
ADF4211/ADF4212, RF: 1750 MHz Output12 –80/–82
ADF4211/ADF4212, RF: 1750 MHz Output13 –65/–70
ADF4212/ADF4213, RF: 2400 MHz Output14 –80/–82
See Note 11
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The B Chip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels, TA = 25°C.
5Guaranteed by design. Sample tested to ensure compliance.
6VDD = 3 V; P = 16; RFIN = 900 MHz; IFIN = 540 MHz, TA = 25°C.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See
TPC 16.
8The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
9fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
f
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
REFIN
11Same conditions as listed in Note 10.
12
f
f
f
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
= 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
REFIN
REFIN
REFIN
13
14
Specifications subject to change without notice.
–3–
REV. A
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