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ADF4113HVBCPZ-RL7 PDF预览

ADF4113HVBCPZ-RL7

更新时间： 2024-01-25 06:05:03
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路信息通信管理泵
页数 文件大小 规格书
20页 489K
描述
High Voltage Charge Pump, PLL Synthesizer

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ADF4113HVBCPZ-RL7 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC20,.16SQ,20针数：20
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01风险等级：1.25
Is Samacsys：N其他特性：6-BIT SWALLOW COUNTER:0 TO 63
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：S-XQCC-N20
JESD-609代码：e3长度：4 mm
湿度敏感等级：3功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC20,.16SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电流 (Isup)：11 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：4 mm
Base Number Matches：1

ADF4113HVBCPZ-RL7 数据手册

 浏览型号ADF4113HVBCPZ-RL7的Datasheet PDF文件第3页浏览型号ADF4113HVBCPZ-RL7的Datasheet PDF文件第4页浏览型号ADF4113HVBCPZ-RL7的Datasheet PDF文件第5页浏览型号ADF4113HVBCPZ-RL7的Datasheet PDF文件第7页浏览型号ADF4113HVBCPZ-RL7的Datasheet PDF文件第8页浏览型号ADF4113HVBCPZ-RL7的Datasheet PDF文件第9页 
ADF4113HV  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
R
V
SET  
P
DV  
CP  
DD  
CPGND  
AGND  
MUXOUT  
LE  
PIN 1  
ADF4113HV  
INDICATOR  
TOP VIEW  
CPGND  
AGND  
AGND  
1
2
3
4
5
15 MUXOUT  
14 LE  
13 DATA  
12 CLK  
11 CE  
(Not to Scale)  
ADF4113HV  
R
R
B
DATA  
CLK  
FIN  
FIN  
TOP VIEW  
RF  
RF  
B
A
IN  
IN  
(Not to Scale)  
A
AV  
CE  
DD  
REF  
DGND  
IN  
Figure 3. TSSOP Pin Configuration  
Figure 4. LFCSP Pin Configuration  
Table 5. Pin Function Descriptions  
TSSOP  
Pin No.  
LFCSP  
Pin No.  
Mnemonic Description  
1
19  
RSET  
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.  
The nominal voltage potential at the RSET pin is 0.56 V for the ADF4113HV. The relationship between  
ICP and RSET is ICPmax = 3/RSET. Therefore, with RSET = 4.7 kΩ, ICPmax = 640 μA.  
2
20  
CP  
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter; in turn, this  
drives the external VCO.  
3
4
5
1
2, 3  
4
CPGND  
AGND  
RFINB  
Charge Pump Ground. CPGND is the ground return path for the charge pump.  
Analog Ground. This is the ground return path of the prescaler.  
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with  
a small bypass capacitor, typically 100 pF.  
6
7
5
6, 7  
RFINA  
AVDD  
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.  
Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the  
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value  
as DVDD.  
8
8
REFIN  
Reference Input. This pin is a CMOS input with a nominal threshold of VDD/2, and an equivalent  
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be  
ac-coupled.  
9
10  
9, 10  
11  
DGND  
CE  
Digital Ground.  
Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output  
into three-state mode. Taking the pin high powers up the device depending on the status of the  
Power-Down Bit PD1.  
11  
12  
CLK  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is  
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS  
input.  
12  
13  
14  
15  
13  
DATA  
LE  
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This  
input is a high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into  
one of the four latches; the latch is selected using the control bits.  
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the  
scaled reference frequency to be externally accessed.  
Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground  
plane (1ꢀF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 ꢀF  
capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical  
but should still be within 5 mm of the pin. DVDD must have the same value as AVDD.  
14  
15  
MUXOUT  
DVDD  
16, 17  
16  
18  
VP  
Charge Pump Power Supply. VP can range from 13.5 V to 16.5 V and should be decoupled  
appropriately.  
Rev. 0 | Page 6 of 20  
 
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