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ADF4113 PDF预览

ADF4113

更新时间: 2024-02-29 03:00:30
品牌 Logo 应用领域
亚德诺 - ADI 射频
页数 文件大小 规格书
24页 263K
描述
RF PLL Frequency Synthesizers

ADF4113 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:5A991.B
HTS代码:8542.39.00.01风险等级:5.41
其他特性:6-BIT SWALLOW COUNTER:0 TO 63模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm湿度敏感等级:1
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:PLL or Frequency Synthesis Circuits
最大供电电流 (Isup):11 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

ADF4113 数据手册

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ADF4110/ADF4111/ADF4112/ADF4113  
PIN FUNCTION DESCRIPTIONS  
Pin No. Mnemonic  
Function  
1
RSET  
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The  
nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is  
23.5  
ICP max  
=
RSET  
So, with RSET = 4.7 k, ICPmax = 5 mA.  
2
CP  
Charge Pump Output. When enabled this provides  
external VCO.  
ICP to the external loop filter, which in turn drives the  
3
4
5
CPGND  
AGND  
RFINB  
Charge Pump Ground. This is the ground return path for the charge pump.  
Analog Ground. This is the ground return path of the prescaler.  
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with  
a small bypass capacitor, typically 100 pF. See Figure 25.  
6
7
RFINA  
AVDD  
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.  
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground  
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD  
.
8
REFIN  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resis-  
tance of 100 k. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or  
it can be ac-coupled.  
9
10  
DGND  
CE  
Digital Ground.  
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-  
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.  
11  
12  
13  
14  
15  
16  
CLK  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into  
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.  
Serial Data Input. The serial data is loaded MSB rst with the two LSBs being the control bits. This  
input is a high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one  
of the four latches, the latch being selected using the control bits.  
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency  
to be accessed externally.  
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground  
DATA  
LE  
MUXOUT  
DVDD  
VP  
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD  
.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,  
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.  
PIN CONFIGURATIONS  
TSSOP  
CHIP SCALE PACKAGE  
1
2
3
4
5
6
7
8
V
P
R
16  
SET  
15 DV  
DD  
CP  
ADF4110  
ADF4111  
ADF4112  
ADF4113  
14 MUXOUT  
13 LE  
CPGND  
AGND  
1
2
3
4
5
15  
14  
13  
12  
11  
CPGND  
AGND  
AGND  
MUXOUT  
LE  
ADF4110  
ADF4111  
ADF4112  
ADF4113  
TOP VIEW 12  
(Not to Scale)  
11  
DATA  
CLK  
RF  
B
A
IN  
IN  
DATA  
CLK  
TOP VIEW  
RF  
RF  
IN  
B
(Not to Scale)  
10  
9
CE  
AV  
DD  
RF  
IN  
A
CE  
DGND  
REF  
IN  
5–  
REV. 0  

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