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ADF4113BRU

更新时间: 2024-11-28 22:05:19
品牌 Logo 应用领域
亚德诺 - ADI 射频
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24页 263K
描述
RF PLL Frequency Synthesizers

ADF4113BRU 数据手册

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a
RF PLL Frequency Synthesizers  
ADF4110/ADF4111/ADF4112/ADF4113  
GENERAL DESCRIPTION  
FEATURES  
The ADF4110 family of frequency synthesizers can be used  
to implement local oscillators in the upconversion and down-  
conversion sections of wireless receivers and transmitters. They  
consist of a low-noise digital PFD (Phase Frequency Detector),  
a precision charge pump, a programmable reference divider,  
programmable A and B counters and a dual-modulus prescaler  
(P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction  
with the dual modulus prescaler (P/P+1), implement an N  
divider (N = BP + A). In addition, the 14-bit reference counter  
(R Counter), allows selectable REFIN frequencies at the PFD  
input. A complete PLL (Phase-Locked Loop) can be imple-  
mented if the synthesizer is used with an external loop filter and  
VCO (Voltage Controlled Oscillator).  
ADF4110: 550 MHz  
ADF4111: 1.2 GHz  
ADF4112: 3.0 GHz  
ADF4113: 4.0 GHz  
2.7 V to 5.5 V Power Supply  
Separate Charge Pump Supply (VP) Allows Extended  
Tuning Voltage in 3 V Systems  
Programmable Dual Modulus Prescaler 8/9, 16/17,  
32/33, 64/65  
Programmable Charge Pump Currents  
Programmable Antibacklash Pulsewidth  
3-Wire Serial Interface  
Analog and Digital Lock Detect  
Hardware and Software Power-Down Mode  
Control of all the on-chip registers is via a simple 3-wire interface.  
The devices operate with a power supply ranging from 2.7 V to  
5.5 V and can be powered down when not in use.  
APPLICATIONS  
Base Stations for Wireless Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Wireless LANS  
Communications Test Equipment  
CATV Equipment  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
DVDD  
VP  
RSET  
CPGND  
REFERENCE  
14-BIT  
R COUNTER  
REFIN  
PHASE  
FREQUENCY  
DETECTOR  
CHARGE  
PUMP  
CP  
14  
R COUNTER  
LATCH  
CLK  
DATA  
LE  
24-BIT  
INPUT REGISTER  
FUNCTION  
LATCH  
LOCK  
DETECT  
CURRENT  
SETTING 1  
CURRENT  
SETTING 2  
22  
A, B COUNTER  
LATCH  
SDOUT  
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4  
19  
FROM  
FUNCTION  
LATCH  
HIGH Z  
AVDD  
13  
MUX  
MUXOUT  
N = BP + A  
13-BIT  
B COUNTER  
SDOUT  
RFIN  
A
LOAD  
LOAD  
PRESCALER  
P/P +1  
RFINB  
6-BIT  
A COUNTER  
M3 M2 M1  
ADF4110/ADF4111  
ADF4112/ADF4113  
6
CE  
AGND  
DGND  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  

ADF4113BRU 替代型号

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