Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R
V
P
SET
DV
CP
15 MUXOUT
14 LE
CPGND
AGND
AGND
1
2
3
4
5
DD
ADF4110
ADF4111
ADF4112
ADF4113
ADF4110
ADF4111
ADF4112
ADF4113
MUXOUT
LE
CPGND
AGND
13 DATA
12 CLK
11 CE
RF
RF
B
A
IN
TOP VIEW
(Not to Scale)
DATA
CLK
RF
RF
B
IN
IN
IN
A
TOP VIEW
(Not to Scale)
CE
AV
DD
DGND
REF
IN
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Function
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
23.5
RSET
ICPmax
=
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn
drives the external VCO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
6
7
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or
can be ac-coupled.
9
10
9, 10
11
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the power-
down Bit F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12
13
14
15
16
13
DATA
LE
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
14
15
MUXOUT
DVDD
VP
16, 17
18
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1
EPAD
Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.
Rev. F | Page 7 of 28
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