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ADF4107BCPZ-REEL

更新时间： 2024-02-09 06:40:03
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 470K
描述
PLL Frequency Synthesizer

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ADF4107BCPZ-REEL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.4
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

ADF4107BCPZ-REEL 数据手册

 浏览型号ADF4107BCPZ-REEL的Datasheet PDF文件第6页浏览型号ADF4107BCPZ-REEL的Datasheet PDF文件第7页浏览型号ADF4107BCPZ-REEL的Datasheet PDF文件第8页浏览型号ADF4107BCPZ-REEL的Datasheet PDF文件第10页浏览型号ADF4107BCPZ-REEL的Datasheet PDF文件第11页浏览型号ADF4107BCPZ-REEL的Datasheet PDF文件第12页 
Data Sheet  
ADF4107  
FUNCTIONAL DESCRIPTION  
REFERENCE INPUT STAGE  
A AND B COUNTERS  
The reference input stage is shown in Figure 17. SW1 and SW2  
are normally closed switches. SW3 is normally open. When  
power-down is initiated, SW3 is closed and SW1 and SW2 are  
opened. This ensures that there is no loading of the REFIN pin  
on power-down.  
The A and B CMOS counters combine with the dual-modulus  
prescaler to allow a wide ranging division ratio in the PLL  
feedback counter. The counters are specified to work when the  
prescaler output is 300 MHz or less. Thus, with an RF input  
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a  
value of 8/9 is not valid.  
POWER-DOWN  
CONTROL  
Pulse Swallow Function  
100kΩ  
SW2  
NC  
The A and B counters, in conjunction with the dual-modulus  
prescaler, make it possible to generate output frequencies that  
are spaced only by the reference frequency divided by R. The  
equation for the VCO frequency is as follows:  
TO R COUNTER  
REF  
IN  
NC  
BUFFER  
SW1  
fREFIN  
R
fVCO  
P BA   
   
SW3  
NO  
where:  
Figure 17. Reference Input Stage  
f
VCO is the output frequency of external voltage controlled  
RF INPUT STAGE  
oscillator (VCO).  
The RF input stage is shown in Figure 18. It is followed by a  
2-stage limiting amplifier to generate the CML clock levels  
needed for the prescaler.  
P is the preset modulus of dual-modulus prescaler (8/9, 16/17).  
B is the preset divide ratio of binary 13-bit counter (3 to 8191).  
A is the preset divide ratio of binary 6-bit swallow counter (0 to 63).  
f
REFIN is the external reference frequency oscillator.  
N = BP + A  
1.6V  
BIAS  
AV  
DD  
GENERATOR  
TO PFD  
13-BIT B  
COUNTER  
500Ω  
500Ω  
LOAD  
FROM RF  
INPUT STAGE  
PRESCALER  
P/P + 1  
LOAD  
RF  
RF  
A
B
IN  
6-BIT A  
COUNTER  
MODULUS  
CONTROL  
IN  
N DIVIDER  
Figure 19. A and B Counters  
AGND  
R COUNTER  
Figure 18. RF Input Stage  
The 14-bit R counter allows the input reference frequency to be  
divided down to produce the reference clock to the phase  
frequency detector (PFD). Division ratios from 1 to 16,383 are  
allowed.  
PRESCALER (P/P + 1)  
The dual-modulus prescaler (P/P + 1), along with the A and B  
counters, enables the large division ratio, N, to be realized  
(N = BP + A). The dual-modulus prescaler, operating at CML  
levels, takes the clock from the RF input stage and divides it  
down to a manageable frequency for the CMOS A and CMOS B  
counters. The prescaler is programmable. It can be set in  
software to 8/9, 16/17, 32/33, or 64/65. It is based on a  
synchronous 4/5 core. A minimum divide ratio is possible for  
fully contiguous output frequencies. This minimum is  
determined by P, the prescaler value, and is given by: (P2 − P).  
PHASE FREQUENCY DETECTOR AND CHARGE PUMP  
The phase frequency detector (PFD) takes inputs from the R  
counter and N counter (N = BP + A) and produces an output  
proportional to the phase and frequency difference between  
them. Figure 20 is a simplified schematic. The PFD includes a  
programmable delay element that controls the width of the  
antibacklash pulse. This pulse ensures that there is no dead zone  
in the PFD transfer function and minimizes phase noise and  
reference spurs. Two bits in the reference counter latch, ABP2  
and ABP1, control the width of the pulse. Use of the minimum  
antibacklash pulse width is not recommended. See Figure 23.  
Rev. D | Page 9 of 20  
 
 
 
 
 
 
 
 
 
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