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ADF4001BCPZ-REEL

更新时间： 2024-02-07 13:48:50

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
16页	189K
描述
IC 200 MHz, OTHER CLOCK GENERATOR, QCC20, LEADLESS FRAME, CSP-20, Clock Generator

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技术参数
数据手册

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ADF4001BCPZ-REEL 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	5A991.B
HTS代码：	8542.39.00.01	风险等级：	0.84
Samacsys Description：	ADF4001BRUZ, PLL Clock Synthesizer, 16-Pin CP 20	其他特性：	ALSO OPERATES AT 5 V NOMINAL SUPPLY
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	主时钟/晶体标称频率：	100 MHz
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压：	5.5 V	最小供电电压：	2.7 V
标称供电电压：	3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER

ADF4001BCPZ-REEL 数据手册

ADF4001

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

R_SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The

nominal voltage potential at the R_SETpin is 0.66 V. The relationship between I_CPand R_SETis

23.5

I_{CP MAX}

R_SET

So, with R_SET= 4.7 kΩ, I_{CP MAX}= 5 mA.

Charge Pump Output. When enabled, this provides

external VCO or VCXO.

I_CPto the external loop filter which, in turn, drives the

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the N Counter. This point must be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 3.

RF_INA

AV_DD

Input to the N Counter. This small signal input is ac-coupled to the external VCO or VCXO.

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AV_DDmust be the same value as DV_DD.

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and a dc equivalent input resis-

tance of 100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or can be

ac-coupled.

DGND

Digital Ground

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking the pin high will power up the device, depending on the status of the power-down bit F2.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This input is a high-impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is

a high-impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.

This multiplexer output allows either the Lock Detect, the scaled RF, or the scaled Reference Frequency to

be accessed externally.

DATA

MUXOUT

DV_DD

V_P

Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV_DDmust be the same value as AV_DD

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems where V_DDis 3 V, it

can be set to 5 V and used to drive a VCO or VCXO with a tuning range of up to 5 V.

PIN CONFIGURATIONS

SET

CPGND

AGND

ADF4001

MUXOUT

PIN 1

15 MUXOUT

14 LE

13 DATA

12 CLK

11 CE

CPGND 1

AGND 2

AGND 3

INDICATOR

ADF4001

TOP VIEW

(Not to Scale)

RF B 4

DATA

CLK

RF A 5

DGND

REF

TRANSISTOR COUNT

6425 (CMOS) and 50 (Bipolar).

–4–

REV. 0

1 2 345 6 7...16

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