ADDC02808PB
SYSTEM INSTABILITY CONSIDERATIONS
LISN requirement, one possible solution is to place a capacitor
across the input of the POL converter. Another possibility is to
place a small resistor in series with this extra capacitor.
In a distributed power supply architecture, a power source pro-
vides power to many “point-of-load” (POL) converters. At low
frequencies, the POL converters appear incrementally as nega-
tive resistance loads. This negative resistance could cause sys-
tem instability problems.
The analysis so far has assumed the source of power was a volt-
age source (e.g., a battery) with some source impedance. In
some cases, this source may be the output of a front-end (FE)
converter. Although each FE converter is different, a model for
a typical one would have an LC output filter driven by a voltage
source whose value was determined by the feedback loop. The
LC filter usually has a high Q, so the compensation of the feed-
back loop is chosen to help dampen any oscillations that result
from load transients. In effect, the feedback loop adds “positive
resistance” to the LC network.
Incremental Negative Resistance: A POL converter is de-
signed to hold its output voltage constant no matter how its
input voltage varies. Given a constant load current, the power
drawn from the input bus is therefore also a constant. If the
input voltage increases by some factor, the input current must
decrease by the same factor to keep the power level constant. In
incremental terms, a positive incremental change in the input
voltage results in a negative incremental change in the input
current. The POL converter therefore looks, incrementally, as a
negative resistor.
When the POL converter is connected to the output of this FE
converter, the POL’s “negative resistance” counteracts the ef-
fects of the FE’s “positive resistance” offered by the feedback
loop. Depending on the specific details, this might simply mean
that the FE converter’s transient response is slightly more oscil-
latory, or it may cause the entire system to be unstable.
The value of this negative resistor at a particular operating
point, VIN , IIN , is:
–VIN
IIN
RN
=
For the ADDC02808PB, LP is approximately 0.5 µH and CP is
approximately 4 µF. Figure 8 shows a more accurate depiction
of the input impedance of the converter as a function of fre-
quency. The negative resistance is, itself, a very good incremen-
tal model for the power state of the converter for frequencies
into the several kHz range (see Figure 8).
Note that this resistance is a function of the operating point. At
full load and low input line, the resistance is its smallest, while
at light load and high input line, it is its largest.
Potential System Instability: The preceding analysis assumes
dc voltages and currents. For ac waveforms the incremental
input model for the POL converter must also include the effects
of its input filter and control loop dynamics. When the POL
converter is connected to a power source, modeled as a voltage
source, VS, in series with an inductor, LS, and some positive
resistor, RS, the network of Figure 37 results.
NAVMAT DERATING
NAVMAT is a Navy power supply reliability manual that is
frequently cited by specifiers of power supplies. A key section
of NAVMAT P4855-1A discusses guidelines for derating designs
and their components. The two key derating criteria are voltage
derating and power derating. Voltage derating is done to reduce
the possibility of electrical breakdown, whereas power derating
is done to maintain the component material below a specified
maximum temperature. While power deratings are typically
stated in terms of current limits (e.g., derate to x% of maximum
rating), NAVMAT also specifies a maximum junction tem-
perature of the semiconductor devices in a power supply. The
NAVMAT component deratings applicable to the ADDC02808PB
are as follows:
L
L
P
R
S
S
INPUT
TERMINALS
V
–|R |
N
C
S
P
ADI DC/DC CONVERTER
Figure 37. Model of Power Source and POL Converter
Connection
Resistors
80% voltage derating
50% power derating
The network shown in Figure 37 is second order and has the
following characteristic equation:
Capacitors
50% voltage and ripple voltage derating
70% ripple current derating
(LS + LP )
s2(LS + LP )C + s
+ RSCP +1 = 0
– R
|
|
N
For the power delivery to be efficient, it is required that RS <<
RN. For the system to be stable, however, the following rela-
tionship must hold:
Transformers and Inductors
60% continuous voltage and current derating
90% surge voltage and current derating
20°C less than rated core temperature
30°C below insulation rating for hot spot temperature
25% insulation breakdown voltage derating
40°C maximum temperature rise
(LS +LP )
(LS +LP )
CP |RN |>
or RS >
CP
R
| |
N
RS
Notice from this result that if (LS + LP) is too large, or if RS is
too small, the system might be unstable. This condition would
first be observed at low input line and full load since the abso-
lute value of RN is smallest at this operating condition.
Transistors
50% power derating
60% forward current (continuous) derating
75% voltage and transient peak voltage derating
110°C maximum junction temperature
If an instability results and it cannot be corrected by changing
LS or RS, such as during the MIL-STD-461D tests due to the
–14–
REV. A
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