Datasheet > ADCS7476_07

ADCS7476_07

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
24页	498K
描述
1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP

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ADCS7476_07 数据手册

Timing Test Circuit

20057708

ADCS7476/ADCS7477/ADCS7478 Timing Specifications

The following specifications apply for V_DD= +2.7V to 5.25V, f_SCLK= 20 MHz, Boldface limits apply for T_A= −40°C to +85°C: all

other limits T_A= 25°C, unless otherwise noted. (Note 9)

Symbol

t_CONVERT

t_QUIET

t₁

Parameter

Conditions

Typical

Limits

Units

16 x t_SCLK

(Note 5)

ns (min)

Minimum CS Pulse Width

CS to SCLK Setup Time

t₂

Delay from CS Until SDATA TRI-STATE

Disabled (Note 6)

t₃

t₄

ns (max)

V_DD= +2.7 to +3.6

ns (max)

ns (min)

Data Access Time after SCLK Falling

Edge(Note 7)

V_DD= +4.75 to +5.25

t₅

t₆

0.4 x t_SCLK

SCLK Low Pulse Width

SCLK High Pulse Width

V_DD= +2.7 to +3.6

t₇

SCLK to Data Valid Hold Time

V_DD= +4.75 to +5.25

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

µs

V_DD= +2.7 to +3.6

SCLK Falling Edge to SDATA High

Impedance (Note 8)

t₈

V_DD= +4.75 to +5.25

t_POWER-UP

Power-Up Time from Full Power-Down

Note 5: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion

Note 6: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.

Note 7: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.

Note 8: t₈is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then adjusted to remove

the effects of charging or discharging the 25pF capacitor. This means t₈is the true bus relinquish time, independent of the bus loading.

Note 9: All input signals are specified as t_r= t_f= 5 ns (10% to 90% V_DD) and timed from 1.6V.

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