Datasheet > ADCMP600BRJZ-REEL7

ADCMP600BRJZ-REEL7

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		比较器
页数	文件大小	规格书
16页	275K
描述
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ADCMP600BRJZ-REEL7 数据手册

浏览型号ADCMP600BRJZ-REEL7的Datasheet PDF文件第2页

浏览型号ADCMP600BRJZ-REEL7的Datasheet PDF文件第3页

浏览型号ADCMP600BRJZ-REEL7的Datasheet PDF文件第4页

浏览型号ADCMP600BRJZ-REEL7的Datasheet PDF文件第6页

浏览型号ADCMP600BRJZ-REEL7的Datasheet PDF文件第7页

浏览型号ADCMP600BRJZ-REEL7的Datasheet PDF文件第8页

ADCMP600/ADCMP601/ADCMP602

TIMING INFORMATION

Figure 2 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown

in Figure 2.

1.1V

LATCH ENABLE

t_S

t_PL

t_H

DIFFERENTIAL

INPUT VOLTAGE

± V

t_PDL

t_PLOH

Q OUTPUT

50%

t_F

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing

Description

t_PDH

t_PDL

t_PLOH

t_PLOL

t_H

Input to output high delay

Propagation delay measured from the time the input signal crosses the reference ( the

input offset voltage) to the 50% point of an output low-to-high transition.

Propagation delay measured from the time the input signal crosses the reference ( the

input offset voltage) to the 50% point of an output high-to-low transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition.

Input to output low delay

Latch enable to output high delay

Latch enable to output low delay

Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs.

t_PL

t_S

Minimum latch enable pulse width

Minimum setup time

Minimum time that the latch enable signal must be high to acquire an input signal change.

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs.

t_R

Output rise time

Output fall time

Voltage overdrive

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points.

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points.

t_F

V_OD

Difference between the input voltages V_Aand V_B.

Rev. 0 | Page 5 of 16

1 2 3 456 7 8...16

下载PDF

与ADCMP600BRJZ-REEL7相关器件

型号	品牌	描述	获取价格	数据表
ADCMP600BRJZ-RL	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators	获取价格
ADCMP600XKSZ	ADI	IC COMPARATOR, 5000 uV OFFSET-MAX, 3 ns RESPONSE TIME, PDSO5, SC-70, 5 PIN, Comparator	获取价格
ADCMP601	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators	获取价格
ADCMP601_15	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V	获取价格
ADCMP601BKJZ	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V	获取价格
ADCMP601BKSZ-R2	ADI	Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators	获取价格