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ADCMP582BCP-WP PDF预览

ADCMP582BCP-WP

更新时间： 2024-01-22 20:34:34
品牌 Logo 应用领域
亚德诺 - ADI 比较器
页数 文件大小 规格书
16页 416K
描述
Ultrafast SiGe Voltage Comparators

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ADCMP582BCP-WP 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC16,.12SQ,20针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.78
放大器类型：COMPARATOR最大平均偏置电流 (IIB)：30 µA
25C 时的最大偏置电流 (IIB)：30 µA最大输入失调电压：10000 µV
JESD-30 代码：S-XQCC-N16JESD-609代码：e3
长度：3 mm湿度敏感等级：3
负供电电压上限：-6 V标称负供电电压 (Vsup)：-5 V
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC16,.12SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：+-5,3.3 V认证状态：Not Qualified
标称响应时间：0.18 ns座面最大高度：0.9 mm
子类别：Comparator供电电压上限：6 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BIPOLAR温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：3 mm
Base Number Matches：1

ADCMP582BCP-WP 数据手册

 浏览型号ADCMP582BCP-WP的Datasheet PDF文件第4页浏览型号ADCMP582BCP-WP的Datasheet PDF文件第5页浏览型号ADCMP582BCP-WP的Datasheet PDF文件第6页浏览型号ADCMP582BCP-WP的Datasheet PDF文件第8页浏览型号ADCMP582BCP-WP的Datasheet PDF文件第9页浏览型号ADCMP582BCP-WP的Datasheet PDF文件第10页 
ADCMP580/ADCMP581/ADCMP582  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
PIN 1  
PIN 1  
PIN 1  
INDICATOR  
INDICATOR  
INDICATOR  
12 GND  
11 Q  
12 GND  
11 Q  
12 V  
CCO  
V
1
2
3
4
V
1
2
3
4
V
TP  
1
2
3
4
TP  
TP  
11 Q  
10 Q  
V
V
V
P
P
P
ADCMP580  
TOP VIEW  
(Not to Scale)  
ADCMP581  
TOP VIEW  
(Not to Scale)  
ADCMP582  
TOP VIEW  
(Not to Scale)  
V
10 Q  
V
10 Q  
V
N
N
N
V
9
GND  
V
9
GND  
V
9 V  
CCO  
TN  
TN  
TN  
Figure 3. ADCMP580 Pin Configuration  
Figure 4. ADCMP581 Pin Configuration  
Figure 5. ADCMP582 Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
2
VTP  
VP  
Termination Resistor Return Pin for VP Input.  
Noninverting Analog Input.  
3
VN  
Inverting Analog Input.  
±
5, 16  
6
VTN  
VCCI  
LE  
Termination Resistor Return Pin for VN Input.  
Positive Supply Voltage.  
Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input  
of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator  
being placed into latch mode. LE must be driven in complement with LE.  
7
8
LE  
Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes  
at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior  
to the comparator being placed into latch mode. LE must be driven in complement with LE.  
VTT  
Termination Return Pin for the LE/LE Input Pins.  
For the ADCMP580 (CML output stage), this pin should be connected to the GND ground.  
For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential.  
For the ADCMP582 (PECL output stage), this pin should be connected to the VCCO – 2 V termination potential.  
Digital Ground Pin/Positive Logic Power Supply Terminal.  
9, 12  
GND/VCCO  
For the ADCMP580/ADCMP581, this pin should be connected to the GND pin.  
For the ADCMP582, this pin should be connected to the positive logic power VCCO supply.  
Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog  
voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions  
(Pin 6 to Pin 7) for more information.  
Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than  
the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the  
LE/LE descriptions (Pin 6 to Pin 7) for more information.  
10  
11  
Q
Q
13  
1±  
VEE  
HYS  
Negative Power Supply.  
Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply  
with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing  
of the HYS hysteresis control resistor.  
15  
GND  
Analog Ground.  
Heat Sink N/C  
Paddle  
The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left  
floating for optimal electrical isolation between the package handle and the substrate of the die. It can also  
be soldered to the application board if improved thermal and/or mechanical stability is desired.  
Rev. 0 | Page 7 of 16  
 
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