ADCMP582BCP-R2

更新时间： 2024-02-02 06:28:11

品牌	Logo	应用领域
亚德诺 - ADI		比较器放大器放大器电路
页数	文件大小	规格书
16页	416K
描述
Ultrafast SiGe Voltage Comparators

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技术参数
数据手册

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ADCMP582BCP-R2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFN	包装说明：	3 X 3 MM, MO-220VEED-2, LFCSP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.39	放大器类型：	COMPARATOR
最大平均偏置电流 (IIB)：	30 µA	25C 时的最大偏置电流 (IIB)：	30 µA
最大输入失调电压：	10000 µV	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e0	长度：	3 mm
湿度敏感等级：	3	负供电电压上限：	-6 V
标称负供电电压 (Vsup)：	-5 V	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC16,.12SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	240	电源：	+-5,3.3 V
认证状态：	Not Qualified	标称响应时间：	0.18 ns
座面最大高度：	0.9 mm	子类别：	Comparators
供电电压上限：	6 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	AUTOMOTIVE	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	3 mm	Base Number Matches：	1

ADCMP582BCP-R2 数据手册

ADCMP580/ADCMP581/ADCMP582

TIMING INFORMATION

Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the

terms shown in the figure.

LATCH ENABLE

50%

LATCH ENABLE

t_S

t_PL

t_H

DIFFERENTIAL

INPUT VOLTAGE

± V

t_PDL

t_PLOH

Q OUTPUT

50%

t_F

t_PDH

Q OUTPUT

t_PLOL

t_R

Figure 2. Comparator Timing Diagram

Table 2. Timing Descriptions

Symbol

Timing

Description

t_PDH

Input to Output High Delay

Propagation delay measured from the time the input signal crosses the reference

(± the input offset voltage) to the 50% point of an output low-to-high transition.

t_PDL

t_PLOH

t_PLOL

t_H

Input to Output Low Delay

Propagation delay measured from the time the input signal crosses the reference

(± the input offset voltage) to the 50% point of an output high-to-low transition.

Propagation delay measured from the 50% point of the latch enable signal

low-to-high transition to the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal

low-to-high transition to the 50% point of an output high-to-low transition.

Minimum time after the negative transition of the latch enable signal that the

input signal must remain unchanged to be acquired and held at the outputs.

Latch Enable to Output High Delay

Latch Enable to Output Low Delay

Minimum Hold Time

t_PL

t_S

Minimum Latch Enable Pulse Width

Minimum Setup Time

Minimum time that the latch enable signal must be high to acquire an input

signal change.

Minimum time before the negative transition of the latch enable signal that an

input signal change must be present to be acquired and held at the outputs.

t_R

Output Rise Time

Amount of time required to transition from a low to a high output as measured

at the 20% and 80% points.

t_F

Output Fall Time

Amount of time required to transition from a high to a low output as measured

at the 20% and 80% points.

V_N

V_OD

Normal Input Voltage

Voltage Overdrive

Difference between the input voltages V_Pand V_Nfor output true.

Difference between the input voltages V_Pand V_Nfor output false.

Rev. 0 | Page 5 of 16

1 2 3 456 7 8...16

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