Datasheet > ADCMP582_15

ADCMP582_15

更新时间： 2022-02-26 11:56:11

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亚德诺 - ADI		/
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16页	430K
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Ultrafast SiGe Voltage Comparators

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ADCMP582_15 数据手册

ADCMP580/ADCMP581/ADCMP582

TIMING INFORMATION

Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the

terms shown in Figure 2.

LATCH ENABLE

50%

LATCH ENABLE

t_S

t_PL

t_H

DIFFERENTIAL

INPUT VOLTAGE

± V

t_PDL

t_PLOH

Q OUTPUT

50%

t_F

t_PDH

Q OUTPUT

t_PLOL

t_R

Figure 2. Comparator Timing Diagram

Table 2. Timing Descriptions

Symbol

Timing

Description

t_PDH

Input-to-Output High Delay

Propagation delay measured from the time the input signal crosses the reference

(± the input offset voltage) to the 50% point of an output low-to-high transition.

t_PDL

t_PLOH

t_PLOL

t_H

Input-to-Output Low Delay

Propagation delay measured from the time the input signal crosses the reference

(± the input offset voltage) to the 50% point of an output high-to-low transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition.

Minimum time after the negative transition of the latch enable signal that the input

signal must remain unchanged to be acquired and held at the outputs.

Latch Enable-to-Output High Delay

Latch Enable-to-Output Low Delay

Minimum Hold Time

t_PL

t_S

Minimum Latch Enable Pulse Width

Minimum Setup Time

Minimum time that the latch enable signal must be high to acquire an input signal change.

Minimum time before the negative transition of the latch enable signal that an input

signal change must be present to be acquired and held at the outputs.

t_R

t_F

Output Rise Time

Output Fall Time

Amount of time required to transition from a low to a high output as measured at the

20% and 80% points.

Amount of time required to transition from a high to a low output as measured at the

20% and 80% points.

V_N

V_OD

Normal Input Voltage

Voltage Overdrive

Difference between the input voltages V_Pand V_Nfor output true.

Difference between the input voltages V_Pand V_Nfor output false.

Rev. A | Page 5 of 16

1 2 3 456 7 8...16

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