ADC774SH-BI

更新时间： 2024-02-14 01:17:25

品牌	Logo	应用领域
BB		转换器模数转换器微处理器信息通信管理
页数	文件大小	规格书
8页	92K
描述
Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER

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技术参数
数据手册

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ADC774SH-BI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	CERAMIC, DIP-28	Reach Compliance Code：	unknown
风险等级：	5.32	Is Samacsys：	N
最大模拟输入电压：	10 V	最小模拟输入电压：	-10 V
最长转换时间：	8.5 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-CDIP-T28	JESD-609代码：	e0
最大线性误差 (EL)：	0.0183%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	12
功能数量：	1	端子数量：	28
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装等效代码：	DIP28,.6	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5,+-12/+-15 V
认证状态：	Not Qualified	子类别：	Analog to Digital Converters
最大压摆率：	20 mA	标称供电电压：	15 V
表面贴装：	NO	技术：	BICMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

ADC774SH-BI 数据手册

CONVERSION START

of the three digital inputs which control conversion will be

ignored, so that conversion cannot be prematurely termi-

nated or restarted. However, if A_Ochanges state after the

beginning of conversion, any additional start conversion

transition will latch the new state of A_O, possibly resulting

in an incorrect conversion length (8 bits vs 12 bits) for that

conversion.

The converter is commanded to initiate a conversion by a

transition occurring on any of three logic inputs (CE, CS,

and R/C) as shown in Table II. Conversion is initiated by the

last of the three to reach the required state and thus all three

may be dynamically controlled. If necessary, all three may

change state simultaneously, and the nominal delay time is

the same regardless of which input actually starts conver-

sion. If it is desired that a particular input establish the actual

start of conversion, the other two should be stable a mini-

mum of 50ns prior to the transition of that input. Timing

relationships for start of conversion timing are illustrated in

Figure 3. The specifications for timing are contained in

Table IV.

READING OUTPUT DATA

After conversion is initiated, the output data buffers remain

in a high-impedance state until the following four logic

conditions are simultaneously met: R/C high, STATUS low,

CE high, and CS low. Upon satisfaction of these conditions

the data lines are enabled according to the state of inputs

12/8 and A_O. See Figure 4 and Table IV for timing relation-

The STATUS output indicates the current state of the con-

verter by being in a high state only during conversion.

During this time the three-state output buffers remain in a

high-impedance state, and therefore data cannot be read

during conversion. During this period additional transitions

ADC774

1...4 5 678

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