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ADC774SH-BI PDF预览

ADC774SH-BI

更新时间： 2024-01-03 11:00:33
品牌 Logo 应用领域
BB 转换器模数转换器微处理器信息通信管理
页数 文件大小 规格书
8页 92K
描述
Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER

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ADC774SH-BI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：CERAMIC, DIP-28Reach Compliance Code：unknown
风险等级：5.32Is Samacsys：N
最大模拟输入电压：10 V最小模拟输入电压：-10 V
最长转换时间：8.5 µs转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：R-CDIP-T28JESD-609代码：e0
最大线性误差 (EL)：0.0183%标称负供电电压：-15 V
模拟输入通道数量：1位数：12
功能数量：1端子数量：28
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：BINARY, OFFSET BINARY输出格式：PARALLEL, WORD
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP28,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：5,+-12/+-15 V
认证状态：Not Qualified子类别：Analog to Digital Converters
最大压摆率：20 mA标称供电电压：15 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

ADC774SH-BI 数据手册

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Figure 1 illustrates timing when conversion is initiated by an  
R/C pulse which goes low and returns to the high state  
during the conversion. In this case, the three-state outputs  
go to the high-impedance state in response to the falling  
edge of R/C and are enabled for external access of the data  
after completion of the conversion. Figure 2 illustrates the  
timing when conversion is initiated by a positive R/C pulse.  
In this mode the output data from the previous conversion is  
enabled during the positive portion of R/C. A new conver-  
sion is started on the falling edge of R/C, and the three-state  
outputs return to the high-impedance state until the next  
occurrence of a high R/C pulse. Timing specifications for  
stand-alone operation are listed in Table III.  
FULLY CONTROLLED OPERATION  
Conversion Length  
Conversion length (8-bit or 12-bit) is determined by the state  
of the AO input, which is latched upon receipt of a conver-  
sion start transition (described below). If AO is latched high,  
the conversion continues for 8 bits. The full 12-bit conver-  
sion will occur if AO is low. If all 12 bits are read following  
an 8-bit conversion, the 3 LSBs (DB0–DB2) will be low  
(logic 0) and DB3 will be high (logic 1). AO is latched  
because it is also involved in enabling the output buffers. No  
other control inputs are latched.  
CE  
CE  
CS  
tHEC  
tSSR  
tHSR  
tSSC  
CS  
tHRR  
tSRC  
tHSC  
R/C  
R/C  
AO  
tSRR  
tHRC  
AO  
tHAR  
tSAR  
tSAC  
tHAC  
STS  
STS  
tHS  
tHD  
tDSC  
tC  
High-Z  
tDD  
DB11–  
DB0  
High Impedance  
DB11–  
DB0  
Data Valid  
tHL  
FIGURE 3. Conversion Cycle Timing.  
FIGURE 4. Read Cycle Timing.  
SYMBOL  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
tDSC  
tHEC  
tSSC  
tHSC  
tSRC  
tHRC  
tSAC  
tHAC  
tC  
STS Delay from CE  
CE Pulse Width  
60  
30  
20  
20  
0
200  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
50  
50  
50  
50  
50  
0
CS to CE Setup time  
CS low during CE high  
R/C to CE setup  
R/C low during CE high  
AO to CE setup  
AO valid during CE high  
Conversion time  
12-bit cycle at 25°C  
0 to +75°C  
20  
50  
20  
7.5  
8.5  
9.0  
9.5  
5.3  
5.6  
6
µs  
µs  
µs  
µs  
µs  
µs  
–55°C to +125°C  
8-bit cycle at 25°C  
0 to +75°C  
5
–55° to +125°C  
Read Mode  
tDD  
tHD  
tHL  
tSSR  
tSAR  
tHSR  
tHRR  
tHAR  
tHS  
Access time from CE  
Data valid after CE low  
Output float delay  
CS to CE setup  
R/C to CE setup  
CS valid after CE low  
R/C high after CE low  
AO valid after CE low  
STS delay after data valid  
75  
35  
100  
0
150  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25  
50  
0
0
0
50  
150  
375  
TABLE IV. Timing Specifications.  
®
6
ADC774  
1...345678

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