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ADC674AKP

更新时间： 2024-02-06 06:00:47
品牌 Logo 应用领域
BB 转换器微处理器
页数 文件大小 规格书
6页 57K
描述
Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER

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ADC674AKP 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP28,.6Reach Compliance Code：unknown
风险等级：5.92最大模拟输入电压：20 V
转换器类型：A/D CONVERTERJESD-30 代码：R-XDIP-T28
JESD-609代码：e0最大线性误差 (EL)：0.024%
位数：12功能数量：1
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY, OFFSET BINARY
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP28,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：5,+-12/+-15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B (Modified)
子类别：Analog to Digital Converters表面贴装：NO
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

ADC674AKP 数据手册

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STAND-ALONE OPERATION  
SYMBOL  
PARAMETER  
MIN  
TYP  
MAX UNITS  
tHRL  
tDS  
tHDR  
tHS  
tHRH  
tDDR  
Low R/C Pulse Width  
STS Delay from R/C  
50  
ns  
For stand-alone operation, control of the converter is accom-  
plished by a single control line connected to R/C. In this  
mode CS and AO are connected to digital common and CE  
and 12/8 are connected to VLOGIC (+5V). The output data are  
presented as 12-bit words. The stand-alone mode is used in  
systems containing dedicated input ports which do not  
require full bus interface capability.  
200  
1000  
150  
ns  
ns  
ns  
ns  
ns  
Data Valid After R/C Low  
STS Delay After Data Valid  
High R/C Pulse Width  
Data Access Time  
25  
300  
150  
400  
TABLE III. Stand-Alone Mode Timing.  
Conversion is initiated by a high-to-low transition of R/C.  
The three-state data output buffers are enabled when R/C is  
high and STATUS is low. Thus, there are two possible  
modes of operation; conversion can be initiated with either  
positive or negative pulses. In either case, the R/C pulse  
must remain low for a minimum of 50ns.  
FULLY CONTROLLED OPERATION  
Conversion Length  
Conversion length (8-bit or 12-bit) is determined by the state  
of the AO input, which is latched upon receipt of a conver-  
sion start transition (described below). If AO is latched high,  
the conversion continues for 8 bits. The full 12-bit conver-  
sion will occur if AO is low. If all 12 bits are read following  
an 8-bit conversion the 3LSBs (DB0 - DB2) will be low  
(logic 0) and DB3 will be high (logic 1). AO  
is latched because it is also involved in enabling the output  
buffers. No other control inputs are latched.  
Figure 1 illustrates timing when conversion is initiated by an  
R/C pulse which goes low and returns to the high state  
during the conversion. In this case, the three-state outputs go  
to the high-impedance state in response to the falling edge of  
R/C and are enabled for external access of the data after  
completion of the conversion. Figure 2 illustrates the timing  
when conversion is initiated by a positive R/C pulse. In this  
mode, the output data from the previous conversion is  
enabled during the positive portion of R/C. A new conver-  
sion is started on the falling edge of R/C, and the three-state  
outputs return to the high impedance state until the next  
occurrence of a high R/C pulse. Timing specifications for  
stand-alone operation are listed in Table III.  
CONVERSION START  
The converter is commanded to initiate conversion by a  
transition occurring on any of three logic inputs (CE, CS,  
and R/C) as shown in Table II. Conversion is initiated by the  
last of the three to reach the required state and thus all three  
may be dynamically controlled. If necessary, all three may  
change states simultaneously, and the nominal delay time is  
the same regardless of which input actually starts conver-  
sion. If it is desired that a particular input establish the actual  
start of conversion, the other two should be stable a mini-  
mum of 50ns prior to the transition of that input. Timing  
relationships for start of conversion timing are illustrated in  
Figure 3. The specifications for timing are contained in  
Table IV.  
tHRL  
R/C  
tDS  
STATUS  
tC  
tHDR  
tHS  
High-Z State  
Data Valid  
Data Valid  
DB11-DB0  
CE  
tHEC  
FIGURE 1. R/C Pulse Low—Outputs Enabled After Con-  
versions.  
tSSC  
CS  
tSRC  
tHSC  
R/C  
AO  
R/C  
tHRH  
tDS  
tHRC  
STATUS  
tC  
tDDR  
tHDR  
tSAC  
High-Z  
High-Z State  
Data Valid  
tHAC  
DB11-DB0  
STATUS  
tDSC  
tC  
FIGURE 2. R/C Pulse High—Outputs Enabled Only While  
R/C is High.  
High Impedance  
DB11-DB0  
FIGURE 3. Conversion Cycle Timing.  
®
5
ADC674A  
123456

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