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ADC674

更新时间： 2024-02-03 16:59:01
品牌 Logo 应用领域
BB 转换器微处理器
页数 文件大小 规格书
6页 57K
描述
Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER

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ADC674 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP28,.6Reach Compliance Code：unknown
风险等级：5.92最大模拟输入电压：20 V
转换器类型：A/D CONVERTERJESD-30 代码：R-XDIP-T28
JESD-609代码：e0最大线性误差 (EL)：0.024%
位数：12功能数量：1
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY, OFFSET BINARY
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP28,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：5,+-12/+-15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B (Modified)
子类别：Analog to Digital Converters表面贴装：NO
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

ADC674 数据手册

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SYMBOL  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
Convert Mode  
tDSC  
tHEC  
tSSC  
tHSC  
tSRC  
tHRC  
tSAC  
tHAC  
tC  
STS Delay from CE  
60  
30  
20  
20  
0
200  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
CE Pulse Width  
50  
50  
50  
50  
50  
0
CS to CE Setup  
CS Low During CE High  
R/C to CE Setup  
R/C Low During CE High  
AO To CE Setup  
20  
AO Valid During CE high  
Conversion Time, 12 Bit Cycle  
8 Bit Cycle  
50  
9
20  
12  
8
15  
10  
6
Read Mode  
tDD  
Access Time From CE  
Data Valid After CE Low  
Output Float Delay  
75  
35  
100  
0
150  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tHD  
tHL  
25  
tSSR  
tSRR  
tSAR  
tHSR  
tHRR  
tHAR  
tHS  
CS to CE Setup  
50  
0
R/C to CE Setup  
AO to CE Setup  
50  
25  
0
CS Valid After CE Low  
R/C high After CE Low  
AO Valid After CE Low  
STS delay After Data Valid  
0
50  
300  
100  
600  
NOTE: Specifications are at + 25°C and measured at 50% level of transitions.  
TABLE IV. Timing Specifications  
The STATUS output indicates the current state of the con-  
verter by being in a high state only during conversion.  
During this time the three state output buffers remain in a  
high-impedance state, and therefore data cannot be read  
during conversion. During this period additional transitions  
of the three digital inputs which control conversion will be  
ignored, so that conversion cannot be prematurely termi-  
nated or restarted. However, if AO changes state after the  
beginning of conversion, any additional start conversion  
transition will latch the new state of AO, possibly resulting  
in an incorrect conversion length (8 bits vs 12 bits) for that  
conversion.  
CE  
CS  
tSSR  
tHSR  
tHRR  
R/C  
AO  
tSRR  
tSAR  
tHAR  
READING OUTPUT DATA  
STATUS  
DB11-DB0  
tHS  
tHD  
After conversion is initiated, the output data buffers remain  
in a high-impedance state until the following four logic  
conditions are simultaneously met: R/C high, STATUS low,  
CE high, and CS low. Upon satisfaction of these conditions  
the data lines are enabled according to the state of inputs  
12/8 and AO. See Figure 4 and Table IV for timing relation-  
ships and specifications.  
High-Z  
tDD  
Data Valid  
tHL  
FIGURE 4. Read Cycle Timing.  
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN  
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject  
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not  
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.  
®
6
ADC674A  
1...3456

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