Datasheet > ADC614JH

ADC614JH

更新时间： 2024-01-09 21:54:10

品牌	Logo	应用领域
BB		转换器
页数	文件大小	规格书
15页	197K
描述
ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP46, CERAMIC, DIP-46

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ADC614JH 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	CERAMIC, DIP-46	Reach Compliance Code：	unknown
风险等级：	5.89	最大模拟输入电压：	1.25 V
最小模拟输入电压：	-1.25 V	转换器类型：	ADC, FLASH METHOD
JESD-30 代码：	R-CDIP-T46	JESD-609代码：	e0
最大线性误差 (EL)：	0.012%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	14
功能数量：	1	端子数量：	46
最高工作温度：	85 °C	最低工作温度：
输出位码：	2'S COMPLEMENT BINARY, COMPLEMENTARY 2'S COMPLEMENT	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装等效代码：	DIP46,1.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-5.2,+-15 V	认证状态：	Not Qualified
采样速率：	5.12 MHz	采样并保持/跟踪并保持：	SAMPLE
子类别：	Analog to Digital Converters	标称供电电压：	15 V
表面贴装：	NO	技术：	HYBRID
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

ADC614JH 数据手册

the capacitor can acquire the signal in 65ns. The low-bias-

current output buffer is then required to settle to only the

resolution (8 bits) of the first (MSB) flash encoder in 65ns,

while an additional 85ns is allowed for settling to the

resolution (14 bits) of the second (LSB) flash encoder.

Sample/Hold droop appears as only an offset error and does

not effect linearity.

THEORY OF OPERATION

The ADC614 is a two-step subranging analog-to-digital

converter. This architecture is shown in Figure 1. The major

system building blocks are: sample/hold amplifier, MSB

flash encoder, DAC and error amplifier, LSB flash encoder,

digital error corrector, and timing circuits. The ADC614

uses hybrid technology with laser-trimmed integrated cir-

cuits mounted in a multilayer ceramic package to integrate

this complex circuit into a complete analog-to-digital con-

verter subsystem with state-of-the-art performance.

Both the MSB and the LSB flash encoder (ADC) functions

are performed by one 8-bit flash encoder. The DAC voltage

reference is also used to generate reference voltages for the

MSB and LSB encoder to compensate drift errors. Buffering

and scaling amplifiers are laser-trimmed to minimize volt-

age offset errors and optimize gain (input full-scale range)

symmetry.

Conceptually, the subranging technique is simple: sample

and hold the input signal, convert to digital with a coarse

ADC, convert back to analog with a coarse-resolution (but

high-accuracy) DAC, subtract this voltage from the S/H

output, amplify this “remainder,” convert to digital with a

second coarse ADC, and combine the digital output from the

first ADC (MSB) with the digital output from the second

ADC (LSB). In practice, however, achieving high conver-

sion speed without sacrificing accuracy is a difficult task.

The subtraction DAC is an ECL 8-bit resolution monolithic

DAC with 14-bit accuracy. Laser-trimmed thin-film nichrome

resistors and high-speed bipolar circuitry allow the DAC

output to settle to 14-bit accuracy in only 35ns.

A “remainder” or coarse conversion-error voltage is gener-

ated by resistively subtracting the DAC output from the

output of the sample/hold amplifier. Before the second

(LSB) conversion, the “remainder” is amplified by a wideband

fast-settling two-input amplifier with a gain of 32V/V. To

prevent overload on large amplitude transients, the active

input is switched off to blank the amplifier input from the

beginning of the S/H acquisition time to the end of the MSB

encoder update time.

The analog input signal is sampled by a high-speed sample/

hold amplifier with low distortion, fast acquisition time and

very low aperture uncertainty (jitter). A diode bridge sam-

pling switch is used to achieve an acceptable compromise

between speed and accuracy. The diode bridge switching

transients are buffered from the analog input by a high input

impedance buffer amplifier. Since the hold capacitor does

not appear in the feedback of the diode bridge output buffer,

R Strobe

L Strobe

M Strobe

Data

Valid

Convert

Command

T/H

Command

8-Bit

Reg

Timing

Digital

Output

DAC

Latch

MUX

8-Bit

Reg

Encoder

Strobe

Amp

Enable

T/H

Output

Error

Amp

Signal

Input

Digital/

Analog

–

Converter

–

X16

Reference

Track/Hold

A/D Converter

Gain

Adjust

FIGURE 1. ADC614 Block Diagram—A Two-Step Subranging Architecture.

ADC614

1...4 5 678 9 10...15

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与ADC614JH相关器件

型号	品牌	描述	获取价格	数据表
ADC614JHQ	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid,	获取价格
ADC614KH	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP46, CERAM	获取价格
ADC614KHQ	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid,	获取价格
ADC614LH	BB	ADC, Flash Method, 14-Bit, 1 Func, Parallel, Word Access, Hybrid,	获取价格
ADC614LHQ	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid,	获取价格
ADC-6-1R	MINI	Directional Coupler 50Ω 5 to 200 MHz	获取价格

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