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ADC124S051CIMM/NOPB PDF预览

ADC124S051CIMM/NOPB

更新时间: 2024-01-10 21:22:32
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
27页 1370K
描述
4 Channel, 200 ksps to 500 kSPS, 12-Bit A/D Converter 10-VSSOP -40 to 85

ADC124S051CIMM/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:TSSOP, TSSOP10,.19,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:16 weeks
风险等级:0.92最大模拟输入电压:5.25 V
最小模拟输入电压:最长转换时间:4.0625 µs
转换器类型:ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码:S-PDSO-G10
JESD-609代码:e3长度:3 mm
最大线性误差 (EL):0.0269%湿度敏感等级:1
模拟输入通道数量:4位数:12
功能数量:1端子数量:10
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3/5 V认证状态:Not Qualified
采样速率:0.5 MHz采样并保持/跟踪并保持:TRACK
座面最大高度:1.07 mm子类别:Analog to Digital Converters
最大压摆率:2.4 mA最小供电电压:2.7 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

ADC124S051CIMM/NOPB 数据手册

 浏览型号ADC124S051CIMM/NOPB的Datasheet PDF文件第3页浏览型号ADC124S051CIMM/NOPB的Datasheet PDF文件第4页浏览型号ADC124S051CIMM/NOPB的Datasheet PDF文件第5页浏览型号ADC124S051CIMM/NOPB的Datasheet PDF文件第7页浏览型号ADC124S051CIMM/NOPB的Datasheet PDF文件第8页浏览型号ADC124S051CIMM/NOPB的Datasheet PDF文件第9页 
ADC104S101  
SNAS284F FEBRUARY 2005REVISED MARCH 2013  
www.ti.com  
ADC104S101 Timing Specifications  
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500  
ksps to 1 Msps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.  
Parameter  
Test Conditions  
VA = +3.0V  
Typical  
3.5  
0.5  
+4.5  
+1.5  
+4  
Limits(1)  
10  
Units  
tCSU  
tCLH  
tEN  
Setup Time SCLK High to CS Falling Edge  
See(2)  
See(2)  
ns (min)  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
Hold time SCLK Low to CS Falling Edge  
Delay from CS Until DOUT active  
10  
30  
30  
ns (min)  
ns (max)  
ns (max)  
+2  
+16.5  
+15  
+3  
tACC  
Data Access Time after SCLK Falling Edge  
tSU  
tH  
tCH  
tCL  
Data Setup Time Prior to SCLK Rising Edge  
Data Valid SCLK Hold Time  
SCLK High Pulse Width  
10  
10  
ns (min)  
ns (min)  
+3  
0.5 x tSCLK 0.3 x tSCLK ns (min)  
SCLK Low Pulse Width  
0.5 x tSCLK 0.3 x tSCLK ns (min)  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
1.7  
1.2  
Output Falling  
Output Rising  
tDIS  
CS Rising Edge to DOUT High-Impedance  
20  
ns (max)  
1.0  
1.0  
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).  
(2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.  
6
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Copyright © 2005–2013, Texas Instruments Incorporated  
Product Folder Links: ADC104S101  
 

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