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ADC104S051

更新时间: 2024-02-20 12:23:46
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
27页 1299K
描述
ADC084S021 4-Channel, 50 ksps to 200 Ksps, 8-Bit A/D Converter

ADC104S051 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:TSSOP, TSSOP10,.19,20
针数:10Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.41
最大模拟输入电压:5.25 V最小模拟输入电压:
最长转换时间:4.0625 µs转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:S-PDSO-G10JESD-609代码:e3
长度:3 mm最大线性误差 (EL):0.0586%
湿度敏感等级:1模拟输入通道数量:4
位数:10功能数量:1
端子数量:10最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY
输出格式:SERIAL封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP10,.19,20
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified采样速率:0.5 MHz
采样并保持/跟踪并保持:TRACK座面最大高度:1.1 mm
子类别:Analog to Digital Converters标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm

ADC104S051 数据手册

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ADC084S021  
SNAS279E APRIL 2005REVISED MARCH 2013  
www.ti.com  
ADC084S021 Timing Specifications  
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200  
ksps, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.  
(1)  
Symbol  
Parameter  
Conditions  
Typical  
Limits  
10  
Units  
VA  
=
(2)  
(2)  
+3.0V  
tCSU  
Setup Time SCLK High to CS Falling Edge  
VA = +5.0V  
0.5  
+4.5  
+1.5  
+4  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
tCLH  
Hold time SCLK Low to CS Falling Edge  
Delay from CS Until DOUT active  
10  
30  
30  
ns (min)  
ns (max)  
ns (max)  
tEN  
+2  
+16.5  
+15  
+3  
tACC  
Data Access Time after SCLK Falling Edge  
tSU  
tH  
tCH  
tCL  
Data Setup Time Prior to SCLK Rising Edge  
Data Valid SCLK Hold Time  
SCLK High Pulse Width  
10  
10  
ns (min)  
ns (min)  
+3  
0.5 x tSCLK 0.3 x tSCLK ns (min)  
SCLK Low Pulse Width  
0.5 x tSCLK 0.3 x tSCLK ns (min)  
VA = +3.0V  
VA = +5.0V  
VA = +3.0V  
VA = +5.0V  
1.7  
1.2  
Output Falling  
Output Rising  
tDIS  
CS Rising Edge to DOUT High-Impedance  
20  
ns (max)  
1.0  
1.0  
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).  
(2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.  
Timing Diagrams  
Power Down  
Power Up  
Power Up  
Hold  
Track  
Hold  
10  
Track  
CS  
1
2
3
4
5
6
7
8
9
11  
12  
13  
14  
15  
16  
1
2
3
4
5
6
7
8
9
10  
SCLK  
Control register  
b4 b3 b2  
Control register  
b4 b3  
b7  
b6  
b5  
b2  
b1  
b0  
b7  
b6  
b5  
b1  
b0  
DIN  
DOUT  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
DB7 DB6 DB5 DB4 DB3  
Figure 2. ADC084S021 Operational Timing Diagram  
6
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