ADC104S021
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SNAS278H –FEBRUARY 2005–REVISED MARCH 2013
ADC104S021/ADC104S021Q Converter Electrical Characteristics (1)(2) (continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
(3)
Symbol
Parameter
Conditions
Typical
±0.01
2
Limits
Units
IOZH, IOZL TRI-STATE® Leakage Current
±1
4
µA (max)
pF (max)
COUT
TRI-STATE® Output Capacitance
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
2.7
V (min)
VA
Supply Voltage
5.25
V (max)
VA = +5.25V,
fSAMPLE = 200 ksps, fIN = 40 kHz
1.3
0.55
90
1.8
0.7
mA (max)
Supply Current, Normal Mode
(Operational, CS low)
VA = +3.6V,
fSAMPLE = 200 ksps, fIN = 40 kHz
mA (max)
IA
VA = +5.25V,
fSAMPLE = 0 ksps
nA
nA
Supply Current, Shutdown (CS high)
VA = +3.6V,
fSAMPLE = 0 ksps
32
VA = +5.25V
VA = +3.6V
VA = +5.25V
VA = +3.6V
6.9
9.5
2.5
mW (max)
mW (max)
µW
Power Consumption, Normal Mode
(Operational, CS low)
1.94
0.47
0.12
PD
Power Consumption, Shutdown (CS
high)
µW
AC ELECTRICAL CHARACTERISTICS
0.8
3.2
50
200
13
30
70
3
MHz (min)
MHz (max)
ksps (min)
ksps (max)
SCLK cycles
% (min)
(4)
(4)
fSCLK
Clock Frequency
fS
Sample Rate
tCONV
DC
Conversion Time
SCLK Duty Cycle
fSCLK = 3.2 MHz
50
% (max)
tACQ
Track/Hold Acquisition Time
Throughput Time
Full-Scale Step Input
SCLK cycles
SCLK cycles
Acquisition Time + Conversion Time
16
(4) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is
specified under Operating Ratings.
ADC104S021/ADC104S021Q Timing Specifications(1)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50
ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
(2)
Symbol
Parameter
Conditions
VA = +3.0V
Typical
−3.5
−0.5
+4.5
+1.5
+4
Limits
10
Units
(3)
(3)
tCSU
Setup Time SCLK High to CS Falling Edge
ns (min)
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
tCLH
Hold time SCLK Low to CS Falling Edge
Delay from CS Until DOUT active
10
30
ns (min)
ns (max)
tEN
+2
+16.5
+15
tACC
tSU
Data Access Time after SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
30
10
ns (max)
ns (min)
+3
(1) PPAP (Production part Approval Process) documentation of the device technology, process and qualification is available from Texas
Instruments upon request.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.
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