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ADAU1452WBCPZ-RL PDF预览

ADAU1452WBCPZ-RL

更新时间: 2024-01-06 15:06:28
品牌 Logo 应用领域
亚德诺 - ADI 商用集成电路
页数 文件大小 规格书
180页 9219K
描述
SigmaDSP Digital Audio Processor

ADAU1452WBCPZ-RL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
针数:72Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:1.55商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-XQCC-N72JESD-609代码:e3
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:72
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

ADAU1452WBCPZ-RL 数据手册

 浏览型号ADAU1452WBCPZ-RL的Datasheet PDF文件第173页浏览型号ADAU1452WBCPZ-RL的Datasheet PDF文件第174页浏览型号ADAU1452WBCPZ-RL的Datasheet PDF文件第175页浏览型号ADAU1452WBCPZ-RL的Datasheet PDF文件第177页浏览型号ADAU1452WBCPZ-RL的Datasheet PDF文件第178页浏览型号ADAU1452WBCPZ-RL的Datasheet PDF文件第179页 
ADAU1452/ADAU1451/ADAU1450  
Data Sheet  
APPLICATIONS INFORMATION  
Parts Placement  
PCB DESIGN CONSIDERATIONS  
Place all 100 nF bypass capacitors, which are recommended for  
every analog, digital, and PLL power ground pair, as near as  
possible to the ADAU1452/ADAU1451/ADAU1450. Bypass each  
of the AVDD, DVDD, PVDD, and IOVDD supply signals on the  
board with an additional single bulk capacitor (10 μF to 47 μF).  
A solid ground plane is a necessity for maintaining signal integrity  
and minimizing EMI radiation. If the PCB has two ground planes,  
they can be stitched together using vias that are spread evenly  
throughout the board.  
Power Supply Bypass Capacitors  
Keep all traces in the crystal resonator circuit (see Figure 15) as  
short as possible to minimize stray capacitance. Do not connect  
any long board traces to the crystal oscillator circuit components  
because such traces may affect crystal startup and operation.  
Bypass each power supply pin to its nearest appropriate ground  
pin with a single 100 nF capacitor and, optionally, with an addi-  
tional 10 nF capacitor in parallel. Make the connections to each  
side of the capacitor as short as possible, and keep the trace on  
a single layer with no vias. For maximum effectiveness, place the  
capacitor either equidistant from the power and ground pins or,  
when equidistant placement is not possible, slightly nearer to  
the power pin (see Figure 81). Establish the thermal connections  
to the planes on the far side of the capacitor.  
Grounding  
Use a single ground plane in the application layout. Place all  
components in an analog signal path away from digital signals.  
Exposed Pad PCB Design  
The device package includes an exposed pad for improved heat  
dissipation. When designing a board for such a package, give  
special consideration to the following:  
POWER GROUND  
Place a copper layer, equal in size to the exposed pad, on all  
layers of the board, from top to bottom. Connect the copper  
layers to a dedicated copper board layer (see Figure 84).  
CAPACITOR  
TO POWER  
TOP  
GROUND  
POWER  
BOTTOM  
TO GROUND  
VIAS  
COPPER SQUARES  
Figure 81. Recommended Power Supply Bypass Capacitor Layout  
Figure 84. Exposed Pad Layout Example—Side View  
Typically, a single 100 nF capacitor for each power ground pin  
pair is sufficient. However, if there is excessive high frequency  
noise in the system, use an additional 10 nF capacitor in parallel  
(see Figure 82). In that case, place the 10 nF capacitor between  
the devices and the 100 nF capacitor, and establish the thermal  
connections on the far side of the 100 nF capacitor.  
Place vias such that all layers of copper are connected,  
allowing for efficient heat and energy conductivity. For an  
example, see Figure 85, which shows 49 vias arranged in  
a 7 × 7 grid in the pad area.  
VIA TO  
POWER PLANE  
VIA TO  
GROUND PLANE  
100nF  
10nF  
Figure 85. Exposed Pad Layout Example—Top View  
PLL Filter  
Figure 82. Layout for Multiple Power Supply Bypass Capacitors  
To minimize jitter, connect the single resistor and two capacitors  
in the PLL filter to the PLLFILT and PVDD pins with short traces.  
To provide a current reservoir in case of sudden current spikes,  
use a 10 µF capacitor for each named supply (DVDD, AVDD,  
PVDD, and IOVDD) as shown in Figure 83.  
BULK BYPASS CAPACITORS  
3.3V  
AVDD PVDD IOVDD DVDD  
+
+
+
+
10µF  
10µF  
10µF  
10µF  
Figure 83. Bulk Capacitor Schematic  
Rev. C | Page 176 of 180  
 
 
 
 
 
 
 

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