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ADAU1451 PDF预览

ADAU1451

更新时间: 2024-01-10 15:19:50
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
180页 9219K
描述
SigmaDSP Digital Audio Processor

ADAU1451 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
针数:72Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:1.61商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-XQCC-N72JESD-609代码:e3
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:72
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

ADAU1451 数据手册

 浏览型号ADAU1451的Datasheet PDF文件第1页浏览型号ADAU1451的Datasheet PDF文件第2页浏览型号ADAU1451的Datasheet PDF文件第4页浏览型号ADAU1451的Datasheet PDF文件第5页浏览型号ADAU1451的Datasheet PDF文件第6页浏览型号ADAU1451的Datasheet PDF文件第7页 
Data Sheet  
ADAU1452/ADAU1451/ADAU1450  
REVISION HISTORY  
7/14—Rev. B to Rev. C  
Changes to Clock Generators Section..........................................30  
Changes to Master Clock Output Section ...................................31  
Changes to I2C Slave Port Section.................................................35  
Changes to Audio Signal Routing Section...................................43  
Changes to Serial Audio Inputs to DSP Core Section................44  
Changes to Asynchronous Sample Rate Converter Input  
Changes to SCL_M/SCLK_M/MP2 Pin Description,  
Table 23 .............................................................................................19  
Change to PLL Lock Register Section ..........................................96  
Changes to Ordering Guide.........................................................180  
5/14—Rev. A to Rev. B  
Routing Section ...............................................................................49  
Change to Serial Input Ports Section............................................61  
Changes to Asynchronous Sample Rate Converters Section ....68  
Changes to S/PDIF Interface Section and S/PDIF Receiver  
Section ..............................................................................................69  
Changes to Auxiliary Output Mode Section ...............................70  
Change to Digital PDM Microphone Interface Section ............71  
Changes to SigmaDSP Core Section.............................................76  
Changes to Soft Reset Function Section ......................................81  
Changes to Random Access Memory Section.............................83  
Added Table 62 and Table 63.........................................................83  
Changes to Table 84 ......................................................................109  
Changed PLL Loop Filter Section to PLL Filter Section..........176  
Change to EOS/ESD Protection Section....................................177  
Change to PCB Manufacturing Guidelines Section.................179  
Changes to Ordering Guide.........................................................180  
Reorganized Layout ...........................................................Universal  
Added ADAU1452 and ADAU1451 .................................Universal  
Changes to Features Section ............................................................1  
Moved Revision History Section.....................................................3  
Changes to General Description Section.......................................4  
Added Differences Between the ADAU1452, ADAU1451, and  
ADAU1450 Section and Table 1, Renumbered Sequentially .......4  
Added Functional Block Diagram—ADAU1450 Section and  
Figure 2, Renumbered Sequentially................................................5  
Changes to Table 2 ............................................................................6  
Changes to Table 3 ............................................................................7  
Changes to Table 6 ............................................................................9  
Changes to Maximum Power Dissipation Section, Table 19,  
and Table 20 .....................................................................................17  
Added Table 21 and Table 22.........................................................17  
Changes to Figure 12 and Table 23 ...............................................18  
Changes to Overview Section........................................................22  
Change to Clocking Overview Section and Power-Up  
1/14—Rev. 0 to Rev. A  
Changed S/PDIF Transceiver and Receiver Maximum Audio  
Sample Rate from 192 kHz to 96 kHz; Table 9 and Table 10.......9  
Sequence Section.............................................................................24  
Changes to Setting the Master Clock and PLL Mode Section ..27  
Changes to Example PLL Settings Section and Table 25 ...........28  
Changed PLL Loop Filter Section to PLL Filter Section............29  
Changes to PLL Filter Section, Figure 17 Caption, and  
10/13—Revision 0: Initial Version  
Table 26 .............................................................................................29  
Rev. C | Page 3 of 180  
 

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