High Performance
10-bit Display Interface
Preliminary Technical Data
AD9984
FEATURES
FUNCTIONAL BLOCK DIAGRAM
10-bit analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic Gain Matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
10
Auto Clamp
Auto Offset
Level Adjust
Auto Gain
Pr/RedIN 1
Pr/RedIN 0
10
10
10
2:1
MUX
PGA
PGA
PGA
Clamp
Clamp
Clamp
10-bit ADC
Red
Cb/Cr/
OUT
10
Auto Clamp
Auto Offset
Level Adjust
Auto Gain
Y/GreenIN 1
Y/GreenIN 0
2:1
MUX
10-bit ADC
Y/Green
OUT
10
Auto Clamp
Auto Offset
Level Adjust
Auto Gain
External clock input
Pb/BlueIN 1
Pb/BlueIN 0
2:1
MUX
10-bit ADC
Cb/Blue
OUT
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsyncs counter
Hsync 1
Hsync 0
2:1
MUX
DATACK
SOGOUT
Pb-free package
Vsync 1
Vsync 0
2:1
MUX
Sync
Processing
O/E Field
HSOUT
SOGIN 1
SOGIN 0
PLL
2:1
MUX
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
Power Management
VSOUT/A0
EXTCLK/COAST
CLAMP
FILT
REFHI
SDA
SCL
Voltage
Refs
Serial Register
HDTV
REFLO
RGB graphics processing
LCD monitors and projectors
Scan converters
Figure 1.
GENERAL DESCRIPTION
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The AD9984 is a complete 10-bit 170 MSPS monolithic analog
interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full-
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p as well as graphics resolutions up to UXGA
(1600 x 1200 at 60 Hz).
The Auto Offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The Auto
Channel-to-channel gain matching feature can be enabled to
minimize any gain mismatches between the three channels.
The AD9984 includes a 170MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a +1.8V power supply and an
analog input. Three-state CMOS outputs may be powered from
1.8V to 3.3V.
The AD9984 also offers full sync processing for composite sync
and sync-on-green applications. A clamp signal is generated
internally or may be provided by the user through the CLAMP
input pin.
The AD9984’s on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 to
170 MHz. With internal COAST generation, the PLL maintains
its output frequency in the absence of sync input. A 32-step
Fabricated in an advanced CMOS process, the AD9984 is
provided in a space-saving 80-pin Pb- free LQFP surface mount
plastic package and is specified over the 0°C to +70°C
temperature range.
Rev. PrB
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infringements of patents or other rights of third parties that may result from its use.
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