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AD9949KCPRL PDF预览

AD9949KCPRL

更新时间: 2024-02-27 12:43:45
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
36页 775K
描述
12-Bit CCD Signal Processor with Precision Timing Core

AD9949KCPRL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:6 X 6 MM, LEAD FREE, MO-220-VJJD-2, LFCSP-40针数:40
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.77
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-XQCC-N40
JESD-609代码:e3长度:6 mm
湿度敏感等级:3功能数量:1
端子数量:40最高工作温度:85 °C
最低工作温度:-20 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:6 mm
Base Number Matches:1

AD9949KCPRL 数据手册

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AD9949  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
D1  
D2  
D3  
1
30 REFB  
PIN 1  
REFT  
AVSS  
2
3
4
5
6
7
8
9
29  
28  
INDICATOR  
D4  
27 CCDIN  
26  
DRVSS  
DRVDD  
D5  
AVDD  
AD9949  
25 CLI  
TOP VIEW  
24 TCVDD  
23  
D6  
D7  
D8 10  
TCVSS  
22 RGVDD  
21 RG  
Figure 2. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No.  
1 to 4  
5
Mnemonic  
D1 to D4  
DRVSS  
DRVDD  
D5 to D11  
H1  
Type1  
DO  
P
Description  
Data Outputs  
Digital Driver Ground  
Digital Driver Supply  
6
P
7 to 13  
14  
DO  
DO  
DO  
P
Data Outputs (D11 is MSB)  
CCD Horizontal Clock 1  
CCD Horizontal Clock 2  
H1 to H4 Driver Ground  
H1 to H4 Driver Supply  
CCD Horizontal Clock 3  
CCD Horizontal Clock 4  
RG Driver Ground  
CCD Reset Gate Clock  
RG Driver Supply  
Analog Ground for Timing Core  
Analog Supply for Timing Core  
Master Clock Input  
15  
H2  
16  
17  
18  
HVSS  
HVDD  
H3  
P
DO  
DO  
P
DO  
P
P
P
DI  
P
AI  
19  
H4  
20  
21  
RGVSS  
RG  
22  
23  
24  
25  
RGVDD  
TCVSS  
TCVDD  
CLI  
26  
27  
28  
29  
AVDD  
CCDIN  
AVSS  
REFT  
Analog Supply for AFE  
Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)  
Analog Ground for AFE  
Reference Top Decoupling (Decouple with 1.0 µF to AVSS)  
Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)  
3-Wire Serial Load  
3-Wire Serial Data Input  
3-Wire Serial Clock  
Vertical Sync Pulse  
Horizontal Sync Pulse  
Digital Ground  
Digital Supply  
Optional HBLK Input  
P
AO  
AO  
DI  
DI  
DI  
DI  
DI  
P
30  
31  
REFB  
SL  
32  
SDI  
33  
SCK  
34  
VD  
35  
HD  
36  
37  
38  
39  
DVSS  
DVDD  
HBLK  
CLP/PBLK  
D0  
P
DI  
DO  
DO  
CLPOB or PBLK Output  
Data Output LSB  
40  
1 Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.  
Rev. B | Page 7 of 36  
 
 

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