Data Sheet
AD9915
AC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT
20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
=
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REF CLK INPUT
Input frequency range
REF CLK Multiplier Bypassed
Input Frequency Range
Duty Cycle
500
45
2500
55
MHz
%
Maximum fOUT is 0.4 × fSYSCLK
Minimum Differential Input Level
System Clock (SYSCLK) PLL Enabled
VCO Frequency Range
VCO Gain (KV)
Maximum PFD Rate
CLOCK DRIVERS
632
mV p-p
Equivalent to 316 mV swing on each leg
2400
2500
125
MHz
MHz/V
MHz
60
SYNC_CLK Output Driver
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
SYNC_OUT Output Driver
Frequency Range
156
55
MHz
%
ps
45
33
0
50
650
10 pF load
6.5
66
MHz
%
ps
Duty Cycle
CFR2 register, Bit 9 = 1
10 pF load
10 pF load
Rise Time (20% to 80%)
Fall Time (20% to 80%)
DAC OUTPUT CHARACTERISTICS
Output Frequency Range (1st Nyquist
Zone)
1350
1670
ps
1250
MHz
Ω
Output Resistance
50
5
Single-ended (each pin internally terminated to
AVDD (3.3V))
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
pF
20.48
+10
0.6
AVDD +
0.50
mA
% FS
μA
V
Range depends on DAC RSET resistor
−10
AVDD −
0.50
Wideband SFDR
See the Typical Performance Characteristics
section
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
978.2 MHz Output
Narrow-Band SFDR
−67
−66
−59
−60
dBc
dBc
dBc
dBc
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
See the Typical Performance Characteristics
section
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
−95
−95
−95
−92
dBc
dBc
dBc
dBc
500 kHz
500 kHz
500 kHz
500 kHz
978.2 MHz Output
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
45
ns
Power-down mode loses DAC/PLL calibration
settings
Time Required to Leave Power-Down
Minimum Master Reset time
250
ns
Must recalibrate DAC/PLL
24
SYSCLK cycles
µs
Maximum DAC Calibration Time (tCAL
)
152
fCAL = fSYSCLK/384 USR0 register, Bit 6 = 0; see the
DAC Calibration Output section for formula
Maximum PLL Calibration Time (tREF_CLK
)
16
8
ms
ms
PFD rate = 25 MHz
PFD rate = 50 MHz
Maximum Profile Toggle Rate
1
SYNC_CLK period
Rev. A | Page 5 of 48