AD9915
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ꢀ5% AVDD (3.3V) and DVDD_I/O (3.3V) = 3.3 V ꢀ5% ꢁA = 2ꢀ°C% RSEꢁ = 3.3 kΩ%
OUꢁ = 20 mA% external reference clock frequency = 2.ꢀ GHz with reference clock (REF CLK) multiplier bypassed% unless otherwise noted.
I
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O
DVDD
Min
Typ
Max
Unit
Test Conditions/Comments
3.135 3.30
1.71 1.80
3.135 3.30
3.465
1.89
3.465
V
V
V
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
AVDD (3.3V)
AVDD (1.8V)
SUPPLY CURRENT
IDVDD_I/O
IDVDD
IAVDD(3.3V)
1.71
1.80
1.89
V
Pin 32, Pin 56, Pin 57
See also the total power dissipation specifications
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
20
270
640
mA
mA
mA
IAVDD(1.8V)
148
mA
Pin 32, Pin 56, Pin 57
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled
2138 2797
2237 2890
mW
mW
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
Base DDS Power, PLL Enabled
Linear Sweep Additional Power
Modulus Additional Power
Amplitude Scaler Additional
Power
28
20
138
mW
mW
mW
Manual or automatic
Full Power-Down Mode
400
616
mW
Using either the power-down and enable register or the
EXT_PWR_DWN pin
CMOS LOGIC INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CMOS LOGIC OUTPUTS
Output High Voltage (VOH)
Output High Voltage (VOL)
REF CLK INPUT CHARACTERISTICS
2.0
2.7
DVDD_I/O
0.8
200
V
V
μA
pF
60
3
At VIN = 0 V and VIN = DVDD_I/O
DVDD_I/O
0.4
V
V
IOH = 1 mA
IOL = 1 mA
REF CLK inputs should always be ac-coupled (both single-
ended and differential)
REF CLK Multiplier Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
1
1.4
2
pF
kΩ
V
Single-ended, each pin
Differential
Differential Input Voltage
REF CLK Multiplier Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
0.8
1.5
1.5
V p-p
1
1.4
2
pF
kΩ
V
Single-ended, each pin
Differential
Differential Input Voltage
0.8
V p-p
Rev. A | Page 4 of 48