Datasheet > AD9913BCPZ1

AD9913BCPZ1

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
32页	687K
描述
Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer

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数据手册

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AD9913BCPZ1 数据手册

AD9913

–50

–55

–60

–65

–70

–75

–80

–85

–90

−50

−60

−70

−80

−90

39.88%

99MHz

49MHz

−100

−110

−120

−130

−140

−150

26.58%

10.21%

25MHz

12.5MHz

100

150

200

250

100

10k

100k

10M

100M

SYSTEM CLOCK (MHz)

FREQUENCY (MHz)

Figure 12. Absolute Phase Noise vs. f_OUTUsing the Internal PLL

(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)

Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)

–100

–50

92.3MHz

48.9MHz

23.1MHz

6.1MHz

PLL ×10

REFSPUR

BYPASS

–55

–60

–65

–70

–75

–80

–85

–90

–110

–120

–130

–140

–150

–160

–170

100

10k

100k

10M

100M

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45

f_OUT(% of System Clock)

FREQUENCY (MHz)

Figure 11. Residual Phase Noise vs. f_OUT(PLL Bypassed)

Figure 13. SFDR Without the Internal PLL

(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)

Rev. 0 | Page 9 of 32

1...6 7 8910 11 12...32

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