Preliminary Technical Data
AD9889B
10
9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
G
H
J
K
BOTTOM VIEW
(Not to Scale)
Figure 4. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type1 Description
BGA
LFCSP
LQFP
A1 to A10, B1 to
B10, C9, C10,
D9, D10
39 to 47,
50 to 63, 2
50 to 58, 65 to D[23:0]
78, 2
I
Video Data Input. Digital input in RGB or YCbCr format. Supports
CMOS logic levels from 1.8 V to 3.3 V.
D1
C2
C1
D2
J3
6
6
CLK
I
I
I
I
I
I
Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1%
tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. 1.8 V to 5.0 V CMOS logic
level.
3
3
DE
4
4
HSYNC
VSYNC
EXT_SW
HPD
5
5
18
20
23
25
K3
E2
7
7
S/PDIF
MCLK
I
I
I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the
audio input from a Sony/Philips digital interface. Supports
CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set
to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS.
1.8 V to 3.3 V CMOS logic level.
I2S Audio Data Inputs. These represent the eight channels of
audio (two per input) available through I2S. Supports CMOS
logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. 1.8 V to 3.3 V
CMOS logic level.
E1
8
8
F2, F1, G2, G1
9 to 12
9 to 12
I2S[3:0]
H2
H1
13
14
13
14
SCLK
LRCLK
I
I
J72
262
332
PD/A0
I
K1, K2
21, 22
30, 31
27, 28
24, 25
32
27, 28
37, 38
34, 35
30, 31
40
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
O
O
O
O
O
P
Differential Clock Output. Differential clock output at pixel
clock rate; TMDS logic level.
Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; TMDS logic level.
Differential Output Channel 1. Differential output of the
green data at 10× the pixel clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue
data at 10× the pixel clock rate; TMDS logic level.
K10, J10
K7, K8
K4, K5
H10
Interrupt. Open drain. A 2 kΩ pull-up resistor to the
microcontroller I/O supply is recommended.
1.8 V Power Supply for TMDS Outputs.
19, 23, 29
24, 29, 36, 41
J2, J5, J8, K9
AVDD
Rev. PrA | Page 7 of 12
5秒后页面跳转
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
PCF8574资料解读：主要参数分析、引脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
