AD9851BRSZRL

更新时间： 2024-01-30 05:56:54

品牌	Logo	应用领域
亚德诺 - ADI		模拟IC 信号电路光电二极管数据分配系统
页数	文件大小	规格书
24页	719K
描述
CMOS 180 MHz DDS/DAC Synthesizer

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技术参数
数据手册

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AD9851BRSZRL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.05
Is Samacsys：	N	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e3
长度：	10.2 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	座面最大高度：	2 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.3 mm
Base Number Matches：	1

AD9851BRSZRL 数据手册

AD9851

PIN CONFIGURATION

LSB D0

PGND

D7 MSB/SERIAL LOAD

DGND

23 DVDD

PVCC

AD9851

TOP VIEW

(Not to Scale)

W CLK

FQ UD

REFCLOCK

AGND

AVDD

RESET

IOUT

20 IOUTB

AGND

AVDD

DACBP

VINP

SET

VOUTN

VOUTP

VINN

PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

4–1,

28–25

D0–D7

8-Bit Data Input.The data port for loading the 32-bit frequency and 8-bit phase/control words. D7 = MSB;

D0 = LSB. D7, Pin 25, also serves as the input pin for 40-bit serial data word.



REFCLK Multiplier Ground Connection.



REFCLK Multiplier Positive SupplyVoltage Pin.

Word Load Clock. Rising edge loads the parallel or serial frequency/phase/control words asynchronously

into the 40-bit input register.

PGND

PVCC

W_CLK

FQ_UD

Frequency Update. A rising edge asynchronously transfers the contents of the 40-bit input register to be

acted upon by the DDS core. FQ_UD should be issued when the contents of the input register are known

to contain only valid, allowable data.

REFCLOCK

Reference Clock Input. CMOS/TTL-level pulse train, direct or via the 6



REFCLK Multiplier. In direct

mode, this is also the SYSTEM CLOCK. If the 6



REFCLK Multiplier is engaged, then the output of the

multiplier is the SYSTEM CLOCK.The rising edge of the SYSTEM CLOCK initiates operations.

Analog Ground.The ground return for the analog circuitry (DAC and Comparator).

Positive supply voltage for analog circuitry (DAC and Comparator, Pin 18) and bandgap voltage reference,

Pin 11.

10, 19

AGND

11, 18

_SET

The DAC’s external R

_SETconnection—nominally a 3.92 k



resistor to ground for 10 mA out.This sets

the DAC full-scale output current available from IOUT and IOUTB. R_SET

= 39.93/IOU

Voltage Output Negative.The comparator’s complementary CMOS logic level output.

Voltage Output Positive.The comparator’s true CMOS logic level output.

Voltage Input Negative.The comparator’s inverting input.

Voltage Input Positive.The comparator’s noninverting input.

DAC Bypass Connection.This is the DAC voltage reference bypass connection normally NC (NO

CONNECT) for optimum SFDR performance.

VOUTN

VOUTP

VINN

VINP

DACBP

IOUTB

IOUT

The complementary DAC output with same characteristics as IOUT except that IOUTB = (full-scale

output–IOUT). Output load should equal that of IOUT for best SFDR performance.

The true output of the balanced DAC. Current is sourcing and requires current-to-voltage

conversion, usually a resistor or transformer referenced to GND. IOUT = (full-scale output–IOUTB).

Master Reset pin; active high; clears DDS accumulator and phase offset register to achieve 0 Hz and 0°

output phase. Sets programming to parallel mode and disengages the 6



REFCLK Multiplier. Reset does

not clear the 40-bit input register. On power-up, asserting RESET should be the ﬁrst priority before pro-

gramming commences.

RESET

DVDD

DGND

Positive supply voltage pin for digital circuitry.

Digital Ground.The ground return pin for the digital circuitry.

REV. D

–5–

1 2 3 456 7 8...24

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