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AD9833BRM-REEL PDF预览

AD9833BRM-REEL

更新时间: 2024-02-20 07:55:20
品牌 Logo 应用领域
亚德诺 - ADI DSP外围设备微控制器和处理器外围集成电路光电二极管时钟
页数 文件大小 规格书
24页 694K
描述
Low Power, 12.65 mW, 2.3 V to 5.5 V Programmable Waveform Generator

AD9833BRM-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP10,.19,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.6
边界扫描:NO最大时钟频率:25 MHz
JESD-30 代码:S-PDSO-G10JESD-609代码:e3
长度:3 mm低功率模式:YES
湿度敏感等级:1端子数量:10
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:1.1 mm子类别:DSP Peripherals
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATORBase Number Matches:1

AD9833BRM-REEL 数据手册

 浏览型号AD9833BRM-REEL的Datasheet PDF文件第3页浏览型号AD9833BRM-REEL的Datasheet PDF文件第4页浏览型号AD9833BRM-REEL的Datasheet PDF文件第5页浏览型号AD9833BRM-REEL的Datasheet PDF文件第7页浏览型号AD9833BRM-REEL的Datasheet PDF文件第8页浏览型号AD9833BRM-REEL的Datasheet PDF文件第9页 
AD9833  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
COMP  
VDD  
1
2
3
4
5
10 VOUT  
9
8
7
6
AGND  
FSYNC  
SCLK  
AD9833  
TOP VIEW  
(Not to Scale)  
CAP/2.5V  
DGND  
MCLK  
SDATA  
Figure 5. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1
2
COMP  
VDD  
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.  
Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied  
from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 µF and a 10 µF decoupling capacitor should be connected  
between VDD and AGND.  
3
CAP/2.5V  
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board  
regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is  
connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.  
4
5
DGND  
MCLK  
Digital Ground.  
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The  
output frequency accuracy and phase noise are determined by this clock.  
6
7
8
SDATA  
SCLK  
FSYNC  
Serial Data Input. The 16-bit serial data-word is applied to this input.  
Serial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK.  
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low,  
the internal logic is informed that a new word is being loaded into the device.  
9
10  
AGND  
VOUT  
Analog Ground.  
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor  
is not required because the device has a 200 Ω resistor on board.  
Rev. E | Page 6 of 24  
 

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