5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > DSP 外围设备> AD9833BRM
AD9833BRM PDF预览

AD9833BRM

更新时间： 2024-01-24 17:42:20
品牌 Logo 应用领域
亚德诺 - ADI 数据分配系统
页数 文件大小 规格书
18页 206K
描述
+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS

阅读下载

获取价格

AD9833BRM 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP10,.19,20针数：10
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.6
边界扫描：NO最大时钟频率：25 MHz
JESD-30 代码：S-PDSO-G10JESD-609代码：e3
长度：3 mm低功率模式：YES
湿度敏感等级：1端子数量：10
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP10,.19,20封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：1.1 mm子类别：DSP Peripherals
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATORBase Number Matches：1

AD9833BRM 数据手册

 浏览型号AD9833BRM的Datasheet PDF文件第1页浏览型号AD9833BRM的Datasheet PDF文件第2页浏览型号AD9833BRM的Datasheet PDF文件第3页浏览型号AD9833BRM的Datasheet PDF文件第5页浏览型号AD9833BRM的Datasheet PDF文件第6页浏览型号AD9833BRM的Datasheet PDF文件第7页 
PRELIMINARY TECHNICAL DATA  
AD9833  
ABSOLUTE MAXIMUM RATINGS*  
(TA = +25°C unless otherwise noted)  
Maximum Junction Temperature . . . . . . . . . . . . . . 150°C  
µSOIC Package  
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .206°C/W  
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . 44°C/W  
Lead Temperature, Soldering (10 sec) . . . . . . . . . 300°C  
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . 220°C  
VDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V  
VDD to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V  
AGND to DGND. . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V  
CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V  
Digital I/O Voltage to DGND . –0.3 V to VDD + 0.3 V  
Analog I/O Voltage to AGND . –0.3 V to VDD + 0.3 V  
Operating Temperature Range  
*Stressesabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanent  
damagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice  
at these or any other conditions above those listed in the operational sections of this  
specification is not implied. Exposure to absolute maximum rating conditions for  
extendedperiodsmayaffectdevicereliability.  
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C  
Storage Temperature Range . . . . . . . . . –65°C to +150°C  
ORDERING GUIDE  
Model  
Temperature Range  
Package Description  
Package Option  
AD9833BRM  
–40°C to +85°C  
14-Pin µSOIC  
(Micro Small Outline IC  
)
RM-10  
EVAL-AD9833EB  
Evaluation Board  
PIN CONFIGURATION  
10  
9
1
2
COMP  
VDD  
VOUT  
AGND  
FSYNC  
SCLK  
AD9833  
8
7
6
CAP/2.5V  
DGND  
3
4
5
TOP VIEW  
(Not to Scale)  
SDATA  
MCLK  
PIN DESCRIPTION  
Pin #  
Mnemonic  
Function  
POWER SUPPLY  
2
3
VDD  
Positive power supply for the analog section and the digital interface sections. The on board 2.5 V  
regulator is also supplied from VDD. VDD can have a value from +2.3 V to +5.5 V. A 0.1 µF and  
10 µF decoupling capacitor should be connected between VDD and AGND.  
CAP/2.5V The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from VDD  
using an on board regulator (when VDD exceeds +2.7 V). The regulator requires a decoupling  
capacitor of typically 100 nF, which is connected from CAP/2.5V to DGND. If VDD is equal to  
or less than +2.7 V, CAP/2.5V should be tied directly to VDD.  
4
9
DGND  
AGND  
Digital Ground.  
Analog Ground.  
ANALOG SIGNAL AND REFERENCE  
1
10  
COMP  
VOUT  
A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.  
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An  
external load resistor is not required as the device has a 200W resistor on board.  
DIGITAL INTERFACE AND CONTROL  
5
MCLK  
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of  
MCLK. The output frequency accuracy and phase noise are determined by this clock.  
Serial Data Input. The 16-bit serial data word is applied to this input.  
Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.  
Active Low Control Input. This is the frame synchronisation signal for the input data. When  
FSYNC is taken low, the internal logic is informed that a new word is being loaded into the  
device.  
6
7
8
SDATA  
SCLK  
FSYNC  
–4–  
REV PrG  
1234567...18

下载PDF

与AD9833BRM相关器件

型号 品牌 描述 获取价格 数据表
AD9833BRM-REEL ADI Low Power, 12.65 mW, 2.3 V to 5.5 V Programmable Waveform Generator

获取价格
AD9833BRM-REEL7 ADI Low Power, 12.65 mW, 2.3 V to 5.5 V Programmable Waveform Generator

获取价格
AD9833BRMZ ADI Evaluation Board User Guide

获取价格
AD9833BRMZ-REEL ADI Low Power, 12.65 mW, 2.3 V to 5.5 V Programmable Waveform Generator

获取价格
AD9833BRMZ-REEL7 ADI Low Power, 12.65 mW, 2.3 V to 5.5 V Programmable Waveform Generator

获取价格
AD9833SRMZ-EP-RL7 ADI Low Power, 12.65 mW, 2.3 V to 5.5 V Programmable Waveform Generator

获取价格

与AD9833BRM相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证