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AD9832BRUZ-REEL7

更新时间： 2024-02-10 06:12:01

品牌	Logo	应用领域
亚德诺 - ADI		电信集成电路电信电路光电二极管
页数	文件大小	规格书
28页	527K
描述
25 MHz Direct Digital Synthesizer, Waveform Generator

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技术参数
数据手册

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AD9832BRUZ-REEL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.59
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.1 mm	最大压摆率：	5 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	Base Number Matches：	1

AD9832BRUZ-REEL7 数据手册

Data Sheet

AD9832

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FS ADJUST

REFIN

COMP

AVDD

REFOUT

DVDD

IOUT

AD9832

TOP VIEW

(Not to Scale)

AGND

PSEL0

PSEL1

FSELECT

FSYNC

DGND

MCLK

SCLK

SDATA

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

FS ADJUST

Full-Scale Adjust Control. A resistor (R_SET) is connected between this pin and AGND. This determines the

magnitude of the full-scale DAC current. The relationship between R_SETand the full-scale current is

IOUT_FULL-SCALE= 12.5 × V_REFIN/R_SET, where V_REFIN= 1.21 V nominal and R_SET= 3.9 kΩ typical.

Voltage Reference Input. The AD9832 can be used with either the on-board reference, which is available from

the REFOUT pin, or an external reference. The reference to be used is connected to the REFIN pin. The AD9832

accepts a reference of 1.21 V nominal.

Voltage Reference Output. The AD9832 has an on-board reference of value 1.21 V nominal. The reference is

available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN.

REFOUT should be decoupled with a 10 nF capacitor to AGND.

Positive Power Supply for the Digital Section. A 0.1 µF decoupling capacitor should be connected between

DVDD and DGND. DVDD can have a value of 5 V 10% or 3.3 V 0%.

REFIN

REFOUT

DVDD

DGND

MCLK

Digital Ground.

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. This

clock determines the output frequency accuracy and phase noise.

SCLK

SDATA

FSYNC

Serial Clock, Logic Input. Data is clocked into the AD9832 on each falling SCLK edge.

Serial Data In, Logic Input. The 16-bit serial data-word is applied to this input.

Data Synchronization Signal, Logic Input. When this input goes low, the internal logic is informed that

a new word is being loaded into the device.

FSELECT

Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase

accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSELECT bit. FSELECT

is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If

FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is

transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an

MCLK rising edge. When the bit is being used to select the frequency register, the FSELECT pin should be tied to DGND.

11, 12

PSEL1,

PSEL0

Phase Select Input. The AD9832 has four phase registers. These registers can be used to alter the value being

input to the SIN ROM. The contents of the phase register are added to the phase accumulator output, the inputs

PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the phase register to be used can be

selected using the PSEL0 and PSEL1 bits. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising

MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an

uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. When the phase

registers are being controlled by the PSEL0 and PSEL1 bits, the pins should be tied to DGND.

AGND

IOUT

AVDD

Analog Ground.

Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND.

Positive Power Supply for the Analog Section. A 0.1 µF decoupling capacitor should be connected between

AVDD and AGND. AVDD can have a value of 5 V 10% or 3.3 V 10%.

COMP

Compensation Pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic

capacitor should be connected between COMP and AVDD.

Rev. E | Page 7 of 28

1...4 5 678 9 10...28

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