AD9822

更新时间： 2024-02-08 16:14:58

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
15页	153K
描述
Complete 14-Bit CCD/CIS Signal Processor

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技术参数
数据手册

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AD9822 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.07
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e3
长度：	10.2 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	COMMERCIAL
座面最大高度：	2 mm	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.3 mm
Base Number Matches：	1

AD9822 数据手册

AD9822

INPUT REFERRED NOISE

DEFINITIONS OF SPECIFICATIONS

The rms output noise is measured using histogram techniques.

The ADC output codes’ standard deviation is calculated in LSB,

and converted to an equivalent voltage, using the relationship

1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the

input of the AD9822 by dividing by the PGA gain.

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity error refers to the deviation of each individual

code from a line drawn from “zero scale” through “positive full

scale.” The point used as “zero scale” occurs 1/2 LSB before

the ﬁrst code transition. “Positive full scale” is deﬁned as a level

1 1/2 LSB beyond the last code transition. The deviation is

measured from the middle of each particular code to the true

straight line.

CHANNEL-TO-CHANNEL CROSSTALK

In an ideal 3-channel system, the signal in one channel will not

influence the signal level of another channel. The channel-to-

channel crosstalk speciﬁcation is a measure of the change that

occurs in one channel as the other two channels are varied. In the

AD9822, one channel is grounded and the other two channels

are exercised with full-scale input signals. The change in the

output codes from the ﬁrst channel is measured and compared

with the result when all three channels are grounded. The

difference is the channel-to-channel crosstalk, stated in LSB.

DIFFERENTIAL NONLINEARITY (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every

code must have a ﬁnite width. No missing codes guaranteed to

14-bit resolution indicates that all 16384 codes, respectively,

must be present over all operating ranges.

OFFSET ERROR

APERTURE DELAY

The ﬁrst ADC code transition should occur at a level 1/2 LSB

above the nominal zero scale voltage. The offset error is the

deviation of the actual ﬁrst code transition level from the

ideal level.

The aperture delay is the time delay that occurs from when a

sampling edge is applied to the AD9822 until the actual sample

of the input signal is held. Both CDSCLK1 and CDSCLK2

sample the input signal during the transition from high to low,

so the aperture delay is measured from each clock’s falling edge

to the instant the actual internal sample is taken.

GAIN ERROR

The last code transition should occur for an analog value

1 1/2 LSB below the nominal full-scale voltage. Gain error is

the deviation of the actual difference between ﬁrst and last code

transitions and the ideal difference between the ﬁrst and last

code transitions.

POWER SUPPLY REJECTION

Power Supply Rejection speciﬁes the maximum full-scale change

that occurs from the initial value when the supplies are varied

over the speciﬁed limits.

REV. A

–5–

1 2 3 456 7 8...15

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