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AD9814S PDF预览

AD9814S

更新时间: 2024-02-06 10:04:54
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
7页 121K
描述
14-Bit CCD/CIS Signal Processor

AD9814S 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknown风险等级:5.63
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:17.9 mm
湿度敏感等级:1功能数量:1
端子数量:28最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
认证状态:COMMERCIAL座面最大高度:2.65 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

AD9814S 数据手册

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AD9814S  
6.0  
Table I. Electrical Table:  
Table I  
Conditions 1/  
Unless Otherwise Specified  
Parameter  
Symbol  
RES  
Sub  
Group  
1,2,3  
Limit Min  
14  
Limit Max  
Units  
Bits  
See notes at end of table  
RESOLUTION  
No Missing Codes  
Supply Currents  
IAVDD  
IDRVDD  
PD  
1,2,3  
1,2,3  
1,2,3  
1,2  
80  
10  
mA  
mA  
Power dissipation  
450  
0.3  
0.5  
11  
mW  
Power supply rejection  
PSR  
AVDD= +5.0V ± 0.25V  
%FSR  
%FSR  
LSB  
3
ACCURACY (Entire Signal Path)  
Integral Nonlinearity 2/  
INL  
1,2  
-11  
3
1
-18  
-1  
11  
LSB  
LSB  
ACCURACY (Entire Signal Path)  
Differential Nonlinearity  
1.25  
DNL  
2
-1  
1
LSB  
3
-1  
1.5  
LSB  
mV  
ACCURACY (Entire Signal Path)  
Offset Error  
VOS  
GAIN  
1,2,3  
-104  
104  
ACCURACY (Entire Signal Path)  
Gain Error 3/  
1,2,3  
1,2,3  
1,2,3  
1,2,3  
-5.3  
5.7  
5.3  
5.9  
%FSR  
PGA Gain Ratio 4/  
PGA GAIN  
VREF4  
VREF2  
DIFFERENTIAL VREF  
1.9  
2.1  
V
V
CAPT-CAPB (4V Input Range)  
DIFFERENTIAL VREF  
0.94  
1.06  
CAPT-CAPB (2V Input Range)  
TABLE I NOTES:  
1/  
TA = +25 °C, TA Max = +125 °C, TA Min = -55 °C. AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS, FADCCLK = 6 MHz, FCDSCLK1 = FCDSCLK2 = 2  
MHz, PGA Gain = 1, Input Range = 4V, unless otherwise noted.  
2/  
3/  
4/  
INL is measured using the “fixed endpoint” method, NOT using a “best-fit” calculation.  
The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.  
The PGA Gain is approximately “linear in dB” and follows the equation: PGA Gain = (5.8 / (1 + 4.8 (63 – G) / 63)) where G is the register  
value.  
ASD0016515 Rev. D | Page 4 of 7  

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