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AD9773EB

更新时间： 2024-02-06 13:50:51
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
19页 214K
描述
12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter

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中文翻译

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AD9773EB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：HTFQFP,针数：80
Reach Compliance Code：unknown风险等级：5.77
其他特性：WITH PROGRAMMABLE PLL最大模拟输出电压：1.25 V
最小模拟输出电压：-1 V转换器类型：D/A CONVERTER
输入位码：BINARY, 2'S COMPLEMENT BINARY输入格式：SERIAL
JESD-30 代码：S-PQFP-G80JESD-609代码：e3
长度：12 mm最大线性误差 (EL)：0.0366%
湿度敏感等级：3功能数量：1
端子数量：80最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HTFQFP封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1.2 mm
标称安定时间 (tstl)：0.011 µs标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：12 mmBase Number Matches：1

AD9773EB 数据手册

 浏览型号AD9773EB的Datasheet PDF文件第2页浏览型号AD9773EB的Datasheet PDF文件第3页浏览型号AD9773EB的Datasheet PDF文件第4页浏览型号AD9773EB的Datasheet PDF文件第5页浏览型号AD9773EB的Datasheet PDF文件第6页浏览型号AD9773EB的Datasheet PDF文件第7页 
PRELIMINARY TECHNICAL DATA  
12-Bit, 160 MSPS  
2×/4×/8× Interpolating  
a
Dual TxDAC+® D/A Converter  
Preliminary Technical Data 01-19-01  
AD9773  
FEATURES  
APPLICATIONS  
Communications:  
12 bit Resolution, 160 MSPS Conversion Rate  
Selectable 2×/4×/8× Interpolating Filter  
Programmable Channel Gain and Offset Adjustment  
Fs/2,4,8 Digital Quadrature Modulation Capability  
Direct IF Transmission Mode for 70MHz+ IFs  
Enables Image Rejection Architecture  
Fully Compatible SPI Port  
Analog Quadrature Modulation Architectures  
3G, Multi-Carrier GSM,TDMA, CDMA Systems  
Multi-Level QAM Modulators, Instrumentation  
PRODUCT DESCRIPTION  
The AD9773 is the 12 bit member of the AD977x family of  
pin-compatible, high performance, programmable 2×/4×/8×  
interpolating TxDAC+s. The AD977x family features a serial  
port interface (SPI) providing a high level of programmabil-  
ity thus allowing for enhanced system level options. These  
options include: selectable 2×/4×/8× interpolation filters;  
Fs/2, Fs/4 or Fs/8 digital quadrature modulation with image  
rejection; a direct IF mode; programmable channel gain  
and offset control; programmable internal clock divider;  
straight binary or two’s complement data interface; and a  
single port or dual port data interface.  
Excellent AC Performance  
- SFDR -69dBc @ 2-35MHz  
-WCDMA ACPR -70dB @ IF=16.25 MHz  
Internal PLL Clock Multiplier  
Selectable Internal Clock Divider  
Versatile Clock Input  
-Differential/Single Ended  
-Sine Wave or TTL/CMOS/LVPECL Compatible  
Versatile Input Data Interface  
-2’s Complement/Straight Binary Data Coding  
-Dual Port or Single Port Interleaved Data  
Single +3.3V Supply Operation  
Power Dissipation: <700 mW @ 3.3V  
On-chip 1.2 V Reference, 80-Lead LQFP  
PROGRAMABLE DUAL INTERPOLATION DAC  
WITH IMAGE REJECTION/DIGITAL MODULATION  
I
I DAC  
OUT  
COS  
+
T
E
HALF-BAND  
FILTER #1*  
N
HALF-BAND  
FILTER #2*  
HALF-BAND  
FILTER#3*  
I
C
C
GA  
DA  
FFS  
-/+  
SIN  
DATA  
O
DA  
ASSEMBLER  
22  
22  
12  
12  
22  
22  
I
12  
12  
T
LATCH  
E
FDAC/2,4,8  
F
F
S
I
O
SIN  
+/-  
Q
LATCH  
22  
22  
+
COS  
FILTER  
BYPASS MUX  
I
OUT  
Q DAC  
WRITE  
MUX  
CONTROL  
SELECT  
Ϭ2  
(F  
DAC  
)
CLOCK OUT  
Ϭ2  
Ϭ2  
Ϭ2  
DIFF.  
REFCLK  
PRESCALER  
SPI INTERFACE &  
CONTROL REGISTERS  
-
PHASE DETEC  
TOR & VCO  
*Half-Band Filters also can be configured for "Zero-Stuffing Only"  
PLL CLOCK MULTIPLIER  
AND CLOCK DIVIDER  
REV. PrA  
BLOCK DIAGRAM  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  
1
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中文翻译

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