AD9578
Data Sheet
Bits
Bit Name
Description
PLL1 Modulus
Value[15:6]
The first 10 bits of the 16-bit modulus value. When the 16-bit binary value is 0, the PLL1 Fractional Feedback
Divider[27:0] value is interpreted as a 28-bit fixed point value. When PLL1 Modulus Value[15:0] is nonzero, and
the rational mode bit is set, the feedback divider ratio is calculated by a complicated expression (see Tabl e 26). In
the simplest case, S[1:0] is set to 3 (no phase interpolation), and the feedback divider expression is PLL1
Fractional Feedback Divider[24:9] + (PLL1 Feedback Divider[24:9]/modulus), generating a feedback divider that
is an exact ratio of integers. Note that having a numerator that is larger than the denominator is an invalid
configuration. Also, note that the lower six bits of the modulus value are shared with the lowest six bits of PLL1
Feedback Divider[27:0], which are not otherwise used in rational mode.
9:0
PLL2 CONFIGURATION (REGISTER 8, ADDRESS 0x08)
Table 40. PLL2 Configuration
Bits
Bit Name
Description
PLL2 Integer
Feedback
Divider[7:0]
PLL2 integer feedback divider. This is a fixed point value that contains the integer portion of the feedback
divider. The smallest allowable value of the PLL1 feedback divider is 23.
39:32
PLL2 Fractional
Feedback
Divider[27:6]
PLL2 fractional feedback divider, Bits[27:6]. If PLL2 is in fractional mode, all 28 bits in the PLL2 fractional
feedback divider are used. If PLL1 is in integer mode, the first three bits in this register can be used either for
phase interpolation or for MASH modulation, according to the value of S[1:0]. In fractional mode at full phase
interpolation, the fractional part of the PLL1 feedback divider is 28 bits, for a resolution of 1/(228), or 3.7 × 10−9
or approximately 4 ppb.
31:10
9:4
3
,
PLL2 Fractional
Feedback
Divider[5:0],
PLL2 Modulus
Value[5:0]
In fractional mode, this register contains Bits[5:0] of the PLL2 fractional feedback divider. In rational mode, this
register contains Bits[5:0] of the PLL2 modulus value. This register is not used in integer mode; do not set the
bits in this register to 0 in integer mode.
This bit controls the power supplies to the charge pump and phase frequency detector. Keep this bit set to 1,
the default setting. These subsystems are automatically disabled whenever the corresponding PLL is powered
ENPFD
down via the
pin.
PD1
This bit controls the power supplies to the VCO. Keep this bit set to 1, the default setting. This subsystem is
automatically disabled whenever the corresponding PLL is powered down via the pin.
2
1
0
VCO PU
PD1
This bit controls the power supplies to the feedback divider. Keep this bit set to 1, the default setting. This
Feedback divider
PU
subsystem is automatically disabled whenever the corresponding PLL is powered down via the
pin.
PD1
PLL2 lock IRQ
(SDO changes to
IRQ)
This bit sets the function of the SDO/LOL pin.
0 (default): the SDO/LOL pin function is serial data output (SDO).
1: the SDO/LOL pin function is IRQ, which is used as a loss of lock (LOL) indicator.
PLL2 CONFIGURATION (REGISTER 9, ADDRESS 0x09)
Table 41. PLL2 Configuration
Bits
Bit Name
Description
Order of dither generation. When PLL2 Dither[2:0] is 0, there is no dithering. All nonzero values create dither of
the value stored in PLL2 Dither[2:0]. Dither is a noise shaped random value that is added to the divider fractional
value at each calculation of the modulation, which helps to disperse harmonic spurs resulting from short
modulation sequences. The time average value of dither is always zero, so that the use of dither does not change
the divider value. The use of dither is highly dependent upon the choice of value for Dither Scale[4:0]. For normal
operation, always set PLL2 Dither[2:0] to zero when PLL2 MASH[2:0] is zero. The largest usable value of PLL2
Dither[2:0] is 5. Typically, the value of PLL2 Dither[2:0] is set equal to the value of PLL2 MASH[2:0].
39:37 PLL2 Dither[2:0]
Dither
Scale[4:0]
Dither scale. The dither scale, in bits. The dither value is a signed value of one to five bits in length, depending on
the value chosen for PLL2 Dither[2:0]. To be effective, this value must be scaled up until the amount of dither is
equal to 1/2 LSB of the divider value. The proper dither scale value for the dither is therefore equal to the
number of zeros following the last bit set to 1 in the feedback divider value. Because the dither is a signed value,
Dither Scale[4:0] must always be larger than the PLL2 Dither[2:0] setting.
36:32
Rev. B | Page 40 of 44
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