AD9561JR

更新时间： 2024-02-27 16:06:05

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
8页	275K
描述
Pulse Width Modulator

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技术参数
数据手册

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AD9561JR 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	PLASTIC, SOIC-28
针数：	28	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.84	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e0
长度：	17.9 mm	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP28,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	2.65 mm
子类别：	Other Analog ICs	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.5 mm
Base Number Matches：	1

AD9561JR 数据手册

AD9561

N+1

CLOCK

DATA

CONTROL

FF, XX

00, XX

C0, 10

C0, 0X

80, 0X

40, 0X

00, XX

C0, 0X

E0, 11

FF, XX

DNC

75%

TEM

75%

DEM

75%

DEM

50%

DEM

25%

DEM

DNC

75%

DEM

87%

LEM

100%

DNC

PULSE

N+1

OUTPUT

PULSE N

Figure 1. Pulse Pattern Example

THEORY OF OPERATION

General

LEADING EDGE

MODULATION

The AD9561 is a mixed signal IC designed to provide high-

speed pulse width modulation in laser printers and copiers. It

uses high performance analog circuits to achieve high resolution

pulse control without requiring the excessively high clock rates

of an all digital solution.

TRAILING EDGE

MODULATION

Because of the sensitivity of analog circuits to digital crosstalk,

PCB layout is critical for achieving optimum results. Please read the

layout section at the end of this data sheet and follow suggestions

completely for best performance.

DUAL EDGE

MODULATION

The AD9561 was designed to facilitate either higher effective

resolution or photo-realistic image reproduction on low cost

laser print platforms. Its 8-bit pulse width resolution and pulse

positioning capabilities combine to offer the highest level of gray

shading and resolution enhancement flexibility available. It

also includes an autocalibration circuit to minimize external

components, and eliminates an extra burden on the system

microprocessor.

Figure 2. Modulation Modes

Pulse positioning within the CLOCK period is defined by the

following table:

Table I. Truth Table

SEM/DEM

LEM/TEM

Alignment

The Functional Block Diagram illustrates the analog content,

comprising ramp generators, DACs and comparators that

generate a series of pulses. These pulses are combined in the

output logic to form PWM OUT pulses whose width is propor-

tional to the 8-bit DATA and whose position is determined by

the SEM/DEM and LEM/TEM inputs.

LEM

TEM

DEM

Single-Edge Modulation offers two options in which one edge is

modulated while the other remains fixed relative to the CLOCK.

For Leading-Edge Modulation, the rising edge of the pulse is

delayed from the leading edge of the CLOCK proportional to

DATA, and the falling edge remains fixed at the end of the

CLOCK period. This may also be called “right-hand justified.”

The AD9561 employs a proprietary ramp topology that

eliminates the loss of dynamic range at the ends of the ramp.

The Functional Block Diagram is shown for illustration purposes

only and does not represent the actual implementation.

Modulation Modes

Similarly, Trailing-Edge Modulation has the rising edge fixed

on the beginning of the CLOCK period and the falling edge

delayed proportional to DATA. This can be called “left-hand

justified.”

Positioning the width controlled pulses at the beginning, middle

or end of the CLOCK period, as shown in Figure 2, adds

significantly to the flexibility of the AD9561. This is accom-

plished through control bit SEM/DEM and LEM/TEM. These

acronyms represent Single-Edge Modulation/Dual-Edge

Modulation and Leading-Edge Modulation/Trailing-Edge

Modulation. SEM/DEM and LEM/TEM are collectively

identified as CONTROL.

Dual-Edge Modulation is often called “center justified” because

the delay of both edges varies relative to the CLOCK. With

increasing values for DATA, pulse width increases with its

center remaining constant proportional to the CLOCK.

Like DATA, modulation control inputs SEM/DEM, and

LEM/TEM can be updated at the CLOCK rate up to 60 MHz.

REV. 0

–4–

1 2 345 6 7 8

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