Data Sheet
AD9554
General Configuration (Register 0x0100 to Register 0x010E)
.......................................................................................................72
DPLL_2 Settings for Reference Input D (REFD) (Register
0x0667 to Register 0x0673)........................................................88
IRQ Mask (Register 0x010F to Register 0x011F)....................73
System Clock (Register 0x0200 to Register 0x0208) ..............75
Reference Input A (Register 0x0300 to Register 0x031E)......76
Reference Input B (Register 0x0320 to Register 0x033E)......78
Reference Input C (Register 0x0340 to Register 0x035E)......78
Reference Input D (Register 0x0360 to Register 0x037E) .....78
DPLL_0 Controls (Register 0x0400 to Register 0x041E).......78
DPLL_3 Controls (Register 0x0700 to Register 0x071E) ......88
APLL_3 Configuration (Register 0x0730 to Register 0x0733)
.......................................................................................................88
PLL_3 Output Sync and Clock Distribution (Register 0x0734
to Register 0x073E).....................................................................88
DPLL_3 Settings for Reference Input A (REFA) (Register
0x0740 to Register 0x074C).......................................................88
DPLL_3 Settings for Reference Input B (REFB) (Register
0x074D to Register 0x0759) ......................................................88
APLL_0 Configuration (Register 0x0430 to Register 0x0434)
.......................................................................................................80
DPLL_3 Settings for Reference Input C (REFC) (Register
0x075A to Register 0x0766).......................................................88
Output PLL_0 (APLL_0) Sync and Clock Distribution
(Register 0x0434 to Register 0x043E).......................................81
DPLL_3 Settings for Reference Input D (REFD) (Register
0x0767 to Register 0x0773)........................................................88
DPLL_0 Settings for Reference Input A (REFA) (Register
0x0440 to Register 0x044C).......................................................83
Digital Loop Filter Coefficients (Register 0x0800 to Register
0x0817).........................................................................................89
DPLL_0 Settings for Reference Input B (REFB) (Register
0x044D to Register 0x0459).......................................................84
Common Operational Controls (Register 0x0A00 to Register
0x0A0E)........................................................................................90
DPLL_0 Settings for Reference Input C (REFC) (Register
0x045A to Register 0x0466).......................................................85
IRQ Clearing (Register 0x0A05 to Register 0x0A14) ............92
DPLL_0 Settings for Reference Input D (REFD) (Register
0x0467 to Register 0x0473)........................................................86
PLL_0 Operational Controls (Register 0x0A20 to Register
0x0A24)........................................................................................95
DPLL_1 Controls (Register 0x0500 to Register 0x051E).......87
PLL_1 Operational Controls (Register 0x0A40 to Register
0x0A44)........................................................................................97
APLL_1 Configuration (Register 0x0530 to Register 0x0533)
.......................................................................................................87
PLL_2 Operational Controls (Register 0x0A60 to Register
0x0A64)........................................................................................97
PLL_1 Output Sync and Clock Distribution (Register 0x0534
to Register 0x053E).....................................................................87
PLL_3 Operational Controls (Register 0x0A80 to Register
0x0A84)........................................................................................97
DPLL_1 Settings for Reference Input A (REFA) (Register
0x0540 to Register 0x054C).......................................................87
Voltage Regulator (Register 0x0B00 to Register 0x0B01)......97
Status ReadBack (Register 0x0D00 to Register 0x0D05).......97
IRQ Monitor (Register 0x0D08 to Register 0x0D16) ............99
DPLL_1 Settings for Reference Input B (REFB) (Register
0x054D to Register 0x0559).......................................................87
DPLL_1 Settings for Reference Input C (REFC) (Register
0x055A to Register 0x0566).......................................................87
PLL_0 Read Only Status (Register 0x0D20 to Register
0x0D2A).....................................................................................102
DPLL_1 Settings for Reference Input D (REFD) (Register
0x0567 to Register 0x0573)........................................................87
PLL_1 Read Only Status (Register 0x0D40 to Register
0x0D4A).....................................................................................104
DPLL_2 Controls (Register 0x0600 to Register 0x061E).......87
PLL_2 Read Only Status (Register 0x0D60 to Register
0x0D6A).....................................................................................104
APLL_2 Configuration (Register 0x0630 to Register 0x0633)
.......................................................................................................87
PLL_3 Read Only Status (Register 0x0D80 to Register
0x0D8A).....................................................................................104
PLL_2 Output Sync and Clock Distribution (Register 0x0634
to Register 0x063E).....................................................................88
EEPROM Control (Register 0x0E00 to Register 0x0E03)...104
DPLL_2 Settings for Reference Input A (REFA) (Register
0x0640 to Register 0x064C).......................................................88
EEPROM Storage Sequence (Register 0x0E10 to Register
0x0E61).......................................................................................105
DPLL_2 Settings for Reference Input B (REFB) (Register
0x064D to Register 0x0659).......................................................88
Outline Dimensions......................................................................116
Ordering Guide .........................................................................116
DPLL_2 Settings for Reference Input C (REFC) (Register
0x065A to Register 0x0666).......................................................88
Rev. D | Page 3 of 116
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