AD9523-1
POWER DISSIPATION
Table 3.
Parameter
Min
Typ
Max
Unit Test Conditions/Comments
POWER DISSIPATION
Typical Configuration
Does not include power dissipated in termination resistors
898
984.7 mW
Clock distribution outputs running as follows: 7 LVPECL at 122.88 MHz,
3 LVDS (3.5 mA) at 61.44 MHz, 3 LVDS (3.5 mA) at 245.76 MHz, 1 single-
ended CMOS 10 pF load at 122.88 MHz, 1 differential input reference
at 30.72 MHz; fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1
at 3, and VCO Divider M2 is off; PLL2 BW = 530 kHz
PD, Power-Down
74
98.2
mW
PD pin pulled low, with typical configuration conditions
INCREMENTAL POWER DISSIPATION
Base Typical Configuration
393
434.7 mW
Absolute total power with clock distribution; 1 LVPECL output (OUT0)
running at 122.88 MHz; 1 differential input reference at 30.72 MHz;
fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1 at 3; VCO
Divider M2 is off
Switched to One Input,
Reference Single-Ended Mode
Switched to Two Inputs,
Reference Differential Mode
Switched to Two Inputs,
Reference Single-Ended Mode
VCO Divider M2
Output Distribution, Driver On
LVDS Mode
−28.5 −8
mW
mW
mW
mW
Running at 30.72 MHz
Running at 30.72 MHz
Running at 30.72 MHz
26
44.6
−27.5 −5.1
76
88.3
Incremental power increase VCO Divider M2 (OUT4) from base typical
Incremental power increase (OUT1) from base typical
3.5 mA
29
88
43
141
46
34.8
105.6 mW
50
164
51
mW
Single 3.5 mA LVDS output at 122.88 MHz
Single 3.5 mA LVDS output at 983.04 MHz
Single 7 mA LVDS output at 122.88 MHz
Single 7 mA LVDS output at 983.04 MHz
Single LVPECL output at 122.88 MHz
Single LVPECL output at 983.04 MHz
7 mA
mW
mW
mW
mW
LVPECL Mode
144
159
HSTL Mode
8 mA
44
143
48
153
6.6
9.9
9.9
51
165
55
176
7.9
11.9
11.9
mW
mW
mW
mW
mW
mW
mW
Single 8 mA HSTL output at 122.88 MHz
Single 8 mA HSTL output at 983.04 MHz
Single 16 mA HSTL output at 122.88 MHz
Single 16 mA HSTL output at 983.04 MHz
16 mA
CMOS Mode
Single 3.3 V CMOS output at 15.36 MHz
Dual complementary 3.3V CMOS output at 15.36 MHz
Dual in-phase 3.3V CMOS output at 15.36 MHz
Lower power mode on, (Channel x control register, Bit 4 = 1)
Output Distribution, Driver On
LVDS Mode
3.5 mA
28.5
88
37
98
40.5
100
33.6
mW
Single 3.5 mA LVDS output at 122.88 MHz
Single 3.5 mA LVDS output at 983.04 MHz
Single 7 mA LVDS output at 122.88 MHz
Single 7 mA LVDS output at 983.04 MHz
Single LVPECL output at 122.88 MHz
Single LVPECL output at 983.04 MHz
105.6 mW
42.9 mW
113.7 mW
46
110
7 mA
LVPECL Mode
mW
mW
HSTL Mode
8 mA
34
94
48
153
39.1
108.1 mW
55.2
176
mW
Single 8 mA HSTL output at 122.88 MHz
Single 8 mA HSTL output at 983.04 MHz
Single 16 mA HSTL output at 122.88 MHz
Single 16 mA HSTL output at 983.04 MHz
16 mA
mW
mW
Rev. B | Page 5 of 60