AD9522-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 27
Operational Configurations...................................................... 27
Mode 0: Internal VCO and Clock Distribution................. 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 7
Clock Outputs............................................................................... 7
Timing Characteristics ................................................................ 8
Timing Diagrams ..................................................................... 8
Mode 1: Clock Distribution or External
VCO < 1600 MHz .................................................................. 29
Mode 2: High Frequency Clock Distribution—
CLK or External VCO > 1600 MHz .................................... 31
Phase-Locked Loop (PLL) .................................................... 33
Configuration of the PLL...................................................... 33
Phase Frequency Detector (PFD) ........................................ 33
Charge Pump (CP)................................................................. 34
On-Chip VCO ........................................................................ 34
PLL External Loop Filter....................................................... 34
PLL Reference Inputs............................................................. 34
Reference Switchover............................................................. 35
Reference Divider R............................................................... 35
VCO/VCXO Feedback Divider N: P, A, B, R ..................... 35
Digital Lock Detect (DLD) ................................................... 37
Analog Lock Detect (ALD)................................................... 37
Current Source Digital Lock Detect (CSDLD) .................. 37
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used).............................................................. 9
Clock Output Absolute Phase Noise (Internal VCO Used).. 10
Clock Output Absolute Time Jitter (Clock Generation Using
Internal VCO)............................................................................. 10
Clock Output Absolute Time Jitter (Clock Cleanup
Using Internal VCO).................................................................. 10
Clock Output Absolute Time Jitter (Clock
Generation Using External VCXO) ......................................... 11
CLK
External VCXO/VCO Clock Input (CLK/
)................ 38
Clock Output Additive Time Jitter
Holdover.................................................................................. 38
External/Manual Holdover Mode........................................ 38
Automatic/Internal Holdover Mode.................................... 38
Frequency Status Monitors ................................................... 40
VCO Calibration .................................................................... 41
Zero Delay Operation................................................................ 42
Internal Zero Delay Mode..................................................... 42
External Zero Delay Mode.................................................... 42
Clock Distribution ..................................................................... 43
Operation Modes ................................................................... 43
Clock Frequency Division..................................................... 44
VCO Divider........................................................................... 44
Channel Dividers ................................................................... 44
Synchronizing the Outputs—SYNC Function................... 46
LVDS Output Drivers............................................................ 47
CMOS Output Drivers .......................................................... 48
(VCO Divider Not Used) .......................................................... 11
Clock Output Additive Time Jitter (VCO Divider Used) ..... 12
Serial Control Port—SPI Mode ................................................ 12
Serial Control Port—IꢀC Mode ................................................ 13
PD SYNC
RESET
Pins ..................................................... 14
,
, and
Serial Port Setup Pins: SP1, SP0 ............................................... 14
LD, STATUS, and REFMON Pins............................................ 14
Power Dissipation....................................................................... 15
Absolute Maximum Ratings.......................................................... 16
Thermal Resistance .................................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 20
Terminology .................................................................................... 25
Detailed Block Diagram ................................................................ 26
Rev. 0 | Page 2 of 84
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