Datasheet > AD9523

AD9523

更新时间： 2024-01-21 04:44:46

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
60页	879K
描述
Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

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AD9523 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	72
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	8.04
系列：	952	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-XQCC-N72	JESD-609代码：	e3
长度：	10 mm	负载电容（CL）：	15 pF
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	72
实输出次数：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	最大电源电流（ICC）：	77.7 mA
Same Edge Skew-Max（tskwd）：	0.3 ns	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	10 mm	Base Number Matches：	1

AD9523 数据手册

Jitter Cleaner and Clock Generator with

14 Differential or 29 LVCMOS Outputs

AD9523

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: < 100 ppm (determined by

VCXO reference accuracy)

OSC_IN, OSC_IN

REFA,

REFA

AD9523

Zero delay operation

OUT0,

OUT0

REFB,

REFB

PLL1

PLL2

Input-to-output edge timing: <150 ps

14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

14 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ½ period of VCO

output divider

OUT1,

OUT1

REF_TEST

SCLK/SCL

SDIO/SDA

SDO

CONTROL

OUT12,

OUT12

INTERFACE

Output-to-output skew: <50 ps

(SPI AND I C)

ZERO

DELAY

Duty-cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: −160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I²C-compatible serial control port

Dual PLL architecture

OUT13,

OUT13

14-CLOCK

DISTRIBUTION

EEPROM

ZD_IN, ZD_IN

Figure 1.

GENERAL DESCRIPTION

PLL1

The AD9523 provides a low power, multi-output, clock distribution

function with low jitter performance, along with an on-chip PLL

and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.

Low bandwidth for reference input clock cleanup with

external VCXO

Phase detector rate of 300 kHz to 75 MHz

Redundant reference inputs

Auto and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

The AD9523 is defined to support the clock requirements for

long term evolution (LTE) and multicarrier GSM base station

designs. It relies on an external VCXO to provide the reference

jitter cleanup to achieve the restrictive low phase noise require-

ments necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide

both single-ended and differential operation. When connected

to a recovered system reference clock and a VCXO, the device

generates 14 low noise outputs with a range of 1 MHz to 1 GHz,

and one dedicated buffered output from the input PLL (PLL1).

The frequency and phase of one clock output relative to another

clock output can be varied by means of a divider phase select

function that serves as a jitter-free coarse timing adjustment in

increments that are equal to half the period of the signal

coming out of the VCO.

PLL2

Phase detector rate of up to 250 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

An in-package EEPROM can be programmed through the serial

interface to store user-defined register settings for power-up

and chip reset.

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

Rev. C

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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